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公开(公告)号：US20130219145A1
公开(公告)日：2013-08-22
申请号：US13555894
申请日：2012-07-23
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F8/433 , G06F8/458 , G06F9/522 , G06F12/0828 , G06F12/0842 , G06F12/0859 , G06F12/0875 , G06F2212/452 , G06F2212/621
摘要： A multithreaded processor can concurrently execute a plurality of threads in a processor core. The threads can access a shared main memory through a memory interface; the threads can generate read and write transactions that cause shared main memory access. An incoherency detection module prevents incoherency by maintaining a record of outstanding global writes, and detecting a conflicting global read. A barrier is sequenced with the conflicting global write. The conflicting global read is allowed to proceed after the sequence of the conflicting global write and the barrier are cleared. The sequence can be maintained by a separate queue for each thread of the plurality.
摘要翻译： 多线程处理器可以同时执行处理器核心中的多个线程。 线程可以通过存储器接口访问共享的主存储器; 线程可以生成导致共享主内存访问的读写事务。 不一致性检测模块通过维护未完成的全局写入的记录以及检测冲突的全局读取来防止不连贯性。 随着全局写入冲突，屏障被排序。 在冲突的全局写入和屏障的顺序被清除之后，允许冲突的全局读取继续进行。 该序列可以由多个的每个线程的单独的队列维护。
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2.发明授权Method and apparatus for dynamic allocation of resources to executing threads in a multi-threaded processor 有权用于动态分配资源以在多线程处理器中执行线程的方法和装置公开(公告)号：US07712101B2
公开(公告)日：2010-05-04
申请号：US10949958
申请日：2004-09-24
IPC分类号： G06F9/46
CPC分类号： G06F9/50 , G06F9/5016
摘要： A method and apparatus are provided for dynamically allocating an access bandwidth for one or more resources to threads of a multithreaded processor. The allocation is performed by providing an execution based metric for each thread and providing an access to the resource in dependence on the execution based metrics of the threads. In addition, or alternatively, a resource based metric can be determined and the access to the resource is provided in dependence on the resource based metric.
摘要翻译： 提供了一种用于向多线程处理器的线程动态分配一个或多个资源的访问带宽的方法和装置。 通过为每个线程提供基于执行的度量来执行分配，并且根据线程的基于执行的度量提供对资源的访问。 另外或替代地，可以确定基于资源的度量，并且依赖于基于资源的度量来提供对资源的访问。
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3.发明授权System for providing trace data in a data processor having a pipelined architecture 有权用于在具有流水线架构的数据处理器中提供跟踪数据的系统公开(公告)号：US08775875B2
公开(公告)日：2014-07-08
申请号：US12387152
申请日：2009-04-28
IPC分类号： G06F11/34
CPC分类号： G06F9/382 , G06F9/30076 , G06F9/3012 , G06F9/30145 , G06F9/3836 , G06F9/3842 , G06F9/3867 , G06F9/4881 , G06F11/3476 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention including providing a trace pipeline in parallel to the execution pipeline, providing trace information on whether conditional instructions are complete or not, providing trace information on the interrupt status of the processor, replacing instructions in the processor with functionally equivalent instructions that also produce trace information and modifying the scheduling of instructions in the processor based on the occupancy of the trace output buffer.
摘要翻译： 本发明是一种用于在流水线数据处理器中提供跟踪数据的方法和系统。 本发明的方面包括提供与执行流水线并行的跟踪流水线，提供关于条件指令是否完成的跟踪信息，提供关于处理器的中断状态的跟踪信息，用功能等同的指令替换处理器中的指令， 根据跟踪输出缓冲区的占用量产生跟踪信息并修改处理器中指令的调度。
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4.发明申请System for providing trace data in a data processor having a pipelined architecture 有权用于在具有流水线架构的数据处理器中提供跟踪数据的系统公开(公告)号：US20090287907A1
公开(公告)日：2009-11-19
申请号：US12387152
申请日：2009-04-28
CPC分类号： G06F9/382 , G06F9/30076 , G06F9/3012 , G06F9/30145 , G06F9/3836 , G06F9/3842 , G06F9/3867 , G06F9/4881 , G06F11/3476 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention include providing a trace pipeline in parallel to the execution pipeline, providing trace information on whether conditional instructions complete or not, providing trace information on the interrupt status of the processor, replacing instructions in the processor with functionally equivalent instructions that also produce trace information and modifying the scheduling of instructions in the processor based on the occupancy of a trace output buffer.
摘要翻译： 本发明是一种用于在流水线数据处理器中提供跟踪数据的方法和系统。 本发明的方面包括提供与执行流水线并行的跟踪流水线，提供关于条件指令是否完成的跟踪信息，提供关于处理器的中断状态的跟踪信息，用功能等效的指令替换处理器中的指令，其也产生 跟踪信息，并根据跟踪输出缓冲区的占用率修改处理器中指令的调度。
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公开(公告)号：US09075724B2
公开(公告)日：2015-07-07
申请号：US13555894
申请日：2012-07-23
CPC分类号： G06F12/0815 , G06F8/433 , G06F8/458 , G06F9/522 , G06F12/0828 , G06F12/0842 , G06F12/0859 , G06F12/0875 , G06F2212/452 , G06F2212/621
摘要： A multithreaded processor can concurrently execute a plurality of threads in a processor core. The threads can access a shared main memory through a memory interface; the threads can generate read and write transactions that cause shared main memory access. An incoherency detection module prevents incoherency by maintaining a record of outstanding global writes, and detecting a conflicting global read. A barrier is sequenced with the conflicting global write. The conflicting global read is allowed to proceed after the sequence of the conflicting global write and the barrier are cleared. The sequence can be maintained by a separate queue for each thread of the plurality.
摘要翻译： 多线程处理器可以同时执行处理器核心中的多个线程。 线程可以通过存储器接口访问共享的主存储器; 线程可以生成导致共享主内存访问的读写事务。 不一致性检测模块通过维护未完成的全局写入的记录以及检测冲突的全局读取来防止不连贯性。 随着全局写入冲突，屏障被排序。 在冲突的全局写入和屏障的顺序被清除之后，允许冲突的全局读取继续进行。 该序列可以由多个的每个线程的单独的队列维护。
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公开(公告)号：US08234455B2
公开(公告)日：2012-07-31
申请号：US12586649
申请日：2009-09-25
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F8/433 , G06F8/458 , G06F9/522 , G06F12/0828 , G06F12/0842 , G06F12/0859 , G06F12/0875 , G06F2212/452 , G06F2212/621
摘要： An apparatus for controlling memory access in a multithreaded processor supporting a plurality of threads is provided. The apparatus includes a processor core; a cache memory storing data accessible by each of the plurality of threads; a main memory storing data accessible by a plurality of threads; an incoherency detection module; and a memory arbiter. The incoherency detection module is connected between the processor core and the memory arbiter, and the memory arbiter is connected between the incoherency detection module and the main memory. There is a separate request queue for each thread for read and write requests sent from the cache memory to the memory arbiter. The incoherency detection module stores an indication of a memory address for each write request sent from the cache memory to the main memory in a write address memory, and compares the address of each subsequent read request sent from the cache memory with indications in the write address memory. If the address of the subsequent read request matches an indication, the incoherency detection module inserts a barrier corresponding to the read request into the request queue of the thread to which the matching indication belongs. The memory arbiter prevents the read request from accessing the memory bus until the corresponding barrier has been received by the memory arbiter.
摘要翻译： 提供了一种用于控制支持多个线程的多线程处理器中的存储器访问的装置。 该装置包括处理器核心; 存储可由所述多个线程中的每个线程访问的数据的高速缓冲存储器; 存储可由多个线程访问的数据的主存储器; 不兼容性检测模块; 和记忆仲裁者。 不连续性检测模块连接在处理器核心和存储器仲裁器之间，并且存储器仲裁器连接在不兼容性检测模块和主存储器之间。 每个线程都有一个单独的请求队列，用于从高速缓冲存储器发送到存储器仲裁器的读取和写入请求。 不一致性检测模块在写地址存储器中存储从高速缓存存储器发送到主存储器的每个写入请求的存储器地址的指示，并将从高速缓存存储器发送的每个后续读取请求的地址与写入地址中的指示进行比较 记忆。 如果随后的读取请求的地址与指示匹配，则不一致性检测模块将与读取请求对应的屏障插入匹配指示所属的线程的请求队列中。 存储器仲裁器防止读请求访问存储器总线，直到存储器仲裁器接收到相应的屏障。
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公开(公告)号：US20100257322A1
公开(公告)日：2010-10-07
申请号：US12586649
申请日：2009-09-25
CPC分类号： G06F12/0815 , G06F8/433 , G06F8/458 , G06F9/522 , G06F12/0828 , G06F12/0842 , G06F12/0859 , G06F12/0875 , G06F2212/452 , G06F2212/621
摘要： There is provided an apparatus for controlling memory access in a multithreaded processor supporting a plurality of threads, comprising: a processor core; a cache memory storing data accessible by each of the plurality of threads; a main memory storing data accessible by a plurality of threads; an incoherency detection module; and a memory arbiter, wherein the incoherency detection module is connected between the processor core and the memory arbiter, and the memory arbiter is connected between the incoherency detection module and the main memory and wherein there is a separate request queue for each thread for read and write requests sent from the cache memory to the memory arbiter; wherein, in use, the incoherency detection module stores an indication of a memory address for each write request sent from the cache memory to the main memory in a write address memory, and compares the address of each subsequent read request sent from the cache memory with indications in the write address memory and, if the address of the subsequent read request matches an indication, inserts a barrier corresponding to the read request into the request queue of the thread to which the matching indication belongs, and wherein the memory arbiter prevents the read request from accessing the memory bus until the corresponding barrier has been received by the memory arbiter.
摘要翻译： 提供了一种用于控制支持多个线程的多线程处理器中的存储器访问的装置，包括：处理器核心; 存储可由所述多个线程中的每个线程访问的数据的高速缓冲存储器; 存储可由多个线程访问的数据的主存储器; 不兼容性检测模块; 和存储器仲裁器，其中所述不一致性检测模块连接在所述处理器核心和所述存储器仲裁器之间，并且所述存储器仲裁器连接在所述不一致性检测模块和所述主存储器之间，并且其中存在用于每个线程用于读取的单独的请求队列， 将从高速缓冲存储器发送的写入请求写入存储器仲裁器; 其特征在于，在使用中，所述不一致性检测模块在写入地址存储器中存储从所述高速缓冲存储器发送到所述主存储器的每个写入请求的存储器地址的指示，并将从所述高速缓存存储器发送的每个后续读取请求的地址与 写入地址存储器中的指示，并且如果后续读取请求的地址与指示匹配，则将与读取请求相对应的屏障插入匹配指示所属的线程的请求队列中，并且其中存储器仲裁器防止读取 访问存储器总线的请求直到存储器仲裁器接收到相应的屏障。
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