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公开(公告)号：US09280650B2
公开(公告)日：2016-03-08
申请号：US13877661
申请日：2010-10-15
申请人： James Robert Waldron
发明人： James Robert Waldron
CPC分类号： G06F21/32 , G06K9/00006
摘要： A computing machine including a sensor to capture a fingerprint image from a user and generate a password in response to the user accessing the sensor, a component to create a package of the fingerprint image and the password, and a processor to authenticate the fingerprint image from the package before decrypting an encryption of the password if a request for the password has been received before a predefined time has elapsed.
摘要翻译： 一种计算机，包括用于从用户捕获指纹图像并响应于用户访问传感器而生成密码的传感器，用于创建指纹图像和密码的包的组件，以及处理器，以从 如果在预定义的时间过去之前已经接收到对密码的请求，则在解密密码加密之前的包。
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公开(公告)号：US20060239052A1
公开(公告)日：2006-10-26
申请号：US11113615
申请日：2005-04-25
IPC分类号： H02M1/00
CPC分类号： H01L27/11898 , H01L27/0207
摘要： An apparatus comprising an integrated circuit having (i) a number of regions each pre-diffused and configured to be metal-programmed and (ii) a plurality of pins configured to connect the integrated circuit to a socket. A logic portion may be implemented on the integrated circuit (i) configured to implement integrated circuit operations and (ii) having one or more I/O connections and one or more supply connections. A first group of the pre-diffused regions are metal-programmed and coupled to said I/O connections. A second group of the pre-diffused regions are metal-programmed and coupled to the supply connections.
摘要翻译： 一种包括集成电路的装置，其具有（i）多个区域，每个区域预扩散并被配置为金属编程;以及（ii）多个引脚，被配置为将集成电路连接到插座。 逻辑部分可以在被配置为实现集成电路操作的集成电路（i）上实现，并且（ii）具有一个或多个I / O连接和一个或多个供电连接。 预扩散区域的第一组被金属编程并耦合到所述I / O连接。 第二组预扩散区域是金属编程的，并且耦合到电源连接。
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公开(公告)号：US20060263933A1
公开(公告)日：2006-11-23
申请号：US11133815
申请日：2005-05-20
CPC分类号： H01L27/118 , G06F17/5068 , H01L27/0207 , H01L27/11898 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a chip is disclosed. A first step of the method may involve fabricating the chip only up to and including a first metal layer during a first manufacturing phase such that an input/output (I/O) region of the chip has a plurality of slots, where each of the slots has a plurality of first transistors. A second step of the method may involve designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the first transistors to form a plurality of mixed-signal building block functions. A third step of the method may involve fabricating the chip to add the upper metal layers during a second manufacturing phase.
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4.发明申请Relocatable built-in self test (BIST) elements for relocatable mixed-signal elements 有权可重定位的内置自检（BIST）元素，用于可重定位的混合信号元素公开(公告)号：US20060259841A1
公开(公告)日：2006-11-16
申请号：US11129547
申请日：2005-05-13
IPC分类号： G01R31/28
CPC分类号： G01R31/31704 , G01R31/3167
摘要： An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions is generally configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a first number of the plurality of pre-diffused regions. The BIST function may be formed with a metal mask set placed over a second number of the plurality of pre-diffused regions. The BIST function may be configured to test the mixed-signal function and present a digital signal indicating an operating condition of the mixed-signal function.
摘要翻译： 一种包括平台专用集成电路（ASIC）的基础层，混合信号功能和内置自检（BIST）功能的装置。 平台ASIC的基础层通常包括围绕平台ASIC的外围设置的多个预扩散区域。 每个预扩散区域通常被配置为金属可编程的。 混合信号功能可以包括由设置在多个预扩散区域的第一数量上的金属掩模组形成的两个或更多个子功能。 BIST功能可以形成有放置在多个预扩散区域的第二数量上的金属掩模组。 BIST功能可以被配置为测试混合信号功能并呈现指示混合信号功能的操作条件的数字信号。
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公开(公告)号：US20140310532A1
公开(公告)日：2014-10-16
申请号：US14344369
申请日：2011-09-28
申请人： Valiuddin Y. Ali , Lan Wang , James Robert Waldron
发明人： Valiuddin Y. Ali , Lan Wang , James Robert Waldron
IPC分类号： G06F21/78
CPC分类号： G06F21/6218 , G06F1/26 , G06F12/1408 , G06F21/31 , G06F21/575 , G06F21/78 , G06F21/81 , G06F2212/1052 , G06F2212/402 , H04L9/0863 , H04L9/0869 , H04L9/3242
摘要： An electronic device has a lower power state in which power to a storage device is disabled. Predetermined information stored in a memory is useable to unlock the storage device during a procedure to transition the electronic device from the lower power state to a higher power state. The predetermined information is different from a credential for use in unlocking the storage device.
摘要翻译： 电子设备具有较低的功率状态，其中存储设备的电力被禁用。 存储在存储器中的预定信息可用于在将电子设备从较低功率状态转换到较高功率状态的过程期间解锁存储设备。 预定信息与用于解锁存储设备的证书不同。
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公开(公告)号：US20130198826A1
公开(公告)日：2013-08-01
申请号：US13877661
申请日：2010-10-15
申请人： James Robert Waldron
发明人： James Robert Waldron
IPC分类号： G06F21/32
CPC分类号： G06F21/32 , G06K9/00006
摘要： A computing machine including a sensor to capture a fingerprint image from a user and generate a password in response to the user accessing the sensor, a component to create a package of the fingerprint image and the password, and a processor to authenticate the fingerprint image from the package before decrypting an encryption of the password if a request for the password has been received before a predefined time has elapsed.
摘要翻译： 一种计算机，包括用于从用户捕获指纹图像并响应于用户访问传感器而生成密码的传感器，用于创建指纹图像和密码的包的组件，以及处理器，以从 如果在预定义的时间过去之前已经接收到对密码的请求，则在解密密码加密之前的包。
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公开(公告)号：US07424690B2
公开(公告)日：2008-09-09
申请号：US11005690
申请日：2004-12-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A system and method for designing a complex electronic circuit by simulating blocks of the circuit using various simulators to produce a net list, designing the physical layout of the circuit using a layout tool that produces a layout verses schematic reference file, mapping the reference file to the net list to create a mapping file, and analyzing the mapping file to verify that the layout meets various criteria. Each block may be verified using simulation tools that are appropriate for that piece of the overall circuit, and using conditions that may maximize the strain on the circuit. The results from the simulations are compared to the physical layout to determine if the physical layout is able to properly conduct the electrical signals.
摘要翻译： 一种用于通过使用各种模拟器模拟电路块以产生网络列表来设计复杂电子电路的系统和方法，使用布局工具来设计电路的物理布局，该布局工具产生与示意图参考文件的布局，将参考文件映射到 创建映射文件的网络列表，并分析映射文件以验证布局符合各种标准。 可以使用适合于整个电路的该片的仿真工具来验证每个块，并且使用可以使电路上的应变最大化的条件。 将仿真的结果与物理布局进行比较，以确定物理布局是否能够正确地传导电信号。
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公开(公告)号：US20080046764A1
公开(公告)日：2008-02-21
申请号：US11620794
申请日：2007-01-08
IPC分类号： G06F12/14
CPC分类号： G06F21/6218
摘要： A method of storing sensitive data by generating randomization values, transforming the sensitive data and the randomization values into a result, and storing separate portions of the result on at least two storage devices, such that the sensitive data cannot be disclosed if any one of the storage devices is compromised.
摘要翻译： 一种通过产生随机化值来存储敏感数据的方法，将敏感数据和随机化值变换为结果，并将结果的分离部分存储在至少两个存储设备上，使得如果敏感数据中的任何一个 存储设备受到损害。
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9.发明申请Method of interconnect for multi-slot metal-mask programmable relocatable function placed in an I/O region 失效用于多槽金属掩模可编程可重定位功能的互连方法放置在I / O区域中公开(公告)号：US20060279326A1
公开(公告)日：2006-12-14
申请号：US11120067
申请日：2005-05-02
IPC分类号： H03K19/173
CPC分类号： H01L27/11898 , G06F17/5077 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A method for interconnecting sub-functions of metal-mask programmable functions that includes the steps of (A) forming a base layer of a platform application specific integrated circuit (ASIC) comprising a plurality of pre-diffused regions disposed around a periphery of the platform ASIC, (B) forming two or more sub-functions of a function with a metal mask set placed over a number of the plurality of pre-diffused regions of the platform application specific integrated circuit and (C) configuring one or more connection points in each of the two or more sub-functions such that interconnections between the two or more sub-functions are tool routable in a single layer. Each of the pre-diffused regions is configured to be metal-programmable.
摘要翻译： 一种用于互连金属掩模可编程功能的子功能的方法，其包括以下步骤：（A）形成平台应用专用集成电路（ASIC）的基层，所述平台专用集成电路（ASIC）包括围绕所述平台周围设置的多个预扩散区域 ASIC，（B）形成功能的两个或更多个子功能，其中金属掩模集放置在平台应用专用集成电路的多个预扩散区域的数量上，以及（C）配置一个或多个连接点 两个或更多个子功能中的每一个，使得两个或多个子功能之间的互连是可在单个层中可路由的工具。 每个预扩散区域被配置为金属可编程的。
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公开(公告)号：US20060271901A1
公开(公告)日：2006-11-30
申请号：US11136180
申请日：2005-05-24
CPC分类号： G06F17/5054 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a chip is disclosed. A first step of the method may include fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step generally involves designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form (i) a mixed-signal module and (ii) a digital module, the mixed signal module generating at least one analog signal and at least one digital signal. In a third step, the method may include fabricating the chip to add the upper metal layers.
摘要翻译： 公开了一种芯片的制造方法。 该方法的第一步可以包括仅制造直到并包括第一金属层的芯片，使得芯片的芯区域具有单元阵列，每个单元具有多个晶体管。 第二步通常包括响应于在第一制造开始之后产生的定制设计，在第一金属层之上设计多个上金属层，上金属层互连多个单元以形成（i）混合信号 模块和（ii）数字模块，所述混合信号模块产生至少一个模拟信号和至少一个数字信号。 在第三步骤中，该方法可以包括制造芯片以添加上部金属层。
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