Signal generator
    1.
    发明授权
    Signal generator 失效
    信号发生器

    公开(公告)号:US4193539A

    公开(公告)日:1980-03-18

    申请号:US849383

    申请日:1977-11-07

    CPC分类号: H03K5/15093 H03K23/542

    摘要: A timing generator which may be used for multiple-cycle controllers is disclosed. A Johnson counter which may have a selectively operable delay interposed between successive stages is utilized with an oscillator and a plurality of multiplexers to provide a plurality of timing pulse train cycles. Circuitry is provided to eliminate spurious output signals from the timing generator.

    摘要翻译: 公开了可用于多循环控制器的定时发生器。 利用振荡器和多个复用器来提供可以在连续级之间插入的选择性可操作延迟的约翰逊计数器来提供多个定时脉冲串循环。 提供电路以消除来自定时发生器的杂散输出信号。

    System for operating volatile memory in normal and standby modes
    2.
    发明授权
    System for operating volatile memory in normal and standby modes 失效
    用于在正常和待机模式下操作易失性存储器的系统

    公开(公告)号:US4130899A

    公开(公告)日:1978-12-19

    申请号:US854856

    申请日:1977-11-25

    CPC分类号: G11C11/406

    摘要: A system including first drivers (such as TTL drivers) operatively connected to the control lines of a volatile memory for providing control and refresh functions to the memory in a normal mode, and second drivers (such as CMOS drivers) operatively connected to the control lines for providing refresh functions to the memory in a standby mode. First and second power sources are provided for providing first and second voltage levels to the first and second drivers, respectively. A diode is connected between the first and second power sources to maintain the first and second voltage levels at a predetermined differential from each other in the event that the second power source fails to prevent damage to the second drivers (CMOS) through reverse biasing.

    摘要翻译: 一种系统,包括可操作地连接到易失性存储器的控制线的第一驱动器(例如TTL驱动器),用于以正常模式向存储器提供控制和刷新功能;以及可操作地连接到控制线的第二驱动器(例如CMOS驱动器) 用于在待机模式下向存储器提供刷新功能。 第一和第二电源被提供用于分别向第一和第二驱动器提供第一和第二电压电平。 在第二电源不能通过反向偏置来防止对第二驱动器(CMOS)的损坏的情况下,二极管连接在第一和第二电源之间,以将第一和第二电压电平彼此保持在预定的差分。

    Methods and devices to increase memory device data reliability
    3.
    发明授权
    Methods and devices to increase memory device data reliability 有权
    提高存储器件数据可靠性的方法和设备

    公开(公告)号:US08631294B2

    公开(公告)日:2014-01-14

    申请号:US13019832

    申请日:2011-02-02

    IPC分类号: G06F11/00

    摘要: A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.

    摘要翻译: 将第一数据集写入被识别为具有较高数据可靠性的第一存储器单元,并且将第二数据组写入被识别为具有比第一存储器单元更低的数据可靠性的第二存储器单元。 在一些情况下,第二数据集可以包括有助于读取和/或解码第一数据集的元数据或冗余信息。 写入第二数据集的动作增加了第一数据集的数据可靠性。 第二数据集可以是空模式,例如所有擦除位。