公开(公告)号：US08621309B2

公开(公告)日：2013-12-31

申请号：US12946278

申请日：2010-11-15

申请人： Yuji Shirahige ,  Ryuichi Sunayama

发明人： Yuji Shirahige ,  Ryuichi Sunayama

IPC分类号： G08C25/02

CPC分类号： G06F12/0855 ,  G06F11/1064

摘要： A processor including: a first storage unit that stores data; an error detection unit that detects an occurrence of error in data read out from the first storage unit; a second storage unit that stores data read out from the first storage unit based on a load request; a rerun request generation unit that generates a rerun request of a load request to the first storage unit in the same cycle as the cycle in which error of data is detected when the error detection unit detects the occurrence of error in data read out from the first storage unit by the load request; and an instruction execution unit that retransmits the load request to the first storage unit when data in which error is detected and a rerun request are given.

摘要翻译： 一种处理器，包括：存储数据的第一存储单元; 错误检测单元，其检测从所述第一存储单元读出的数据中的错误的发生; 第二存储单元，其基于加载请求存储从第一存储单元读出的数据; 重新运行请求生成单元，其在与所述错误检测单元检测到从所述第一存储单元读出的数据的错误的发生相同的周期中生成与所述数据的错误相同的周期中的与所述第一存储单元的加载请求的重新运行请求 存储单元通过负载请求; 以及指示执行单元，当在其中检测到错误的数据和给出重新运行请求时，向第一存储单元重传加载请求。

公开(公告)号：US07765387B2

公开(公告)日：2010-07-27

申请号：US10352005

申请日：2003-01-28

申请人： Ryuichi Sunayama ,  Kuniki Morita ,  Aiichiro Inoue

发明人： Ryuichi Sunayama ,  Kuniki Morita ,  Aiichiro Inoue

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/321 ,  G06F9/3842 ,  G06F9/3844

摘要： A program counter control method controls instructions by an out-of-order method using a branch prediction mechanism and controls an architecture having delay instructions for branching. The method includes the steps of simultaneously committing a plurality of instructions including a branch instruction, when a branch prediction is successful and the branch instruction branches, and simultaneously updating a program counter and a next program counter depending on a number of committed instructions.

摘要翻译： 程序计数器控制方法通过使用分支预测机制的无序方法来控制指令，并且控制具有用于分支的延迟指令的架构。 该方法包括以下步骤：当分支预测成功并且分支指令分支时同时提交包括分支指令的多个指令，并且根据所提交的指令的数目同时更新程序计数器和下一个程序计数器。

公开(公告)号：US20050188187A1

公开(公告)日：2005-08-25

申请号：US11114202

申请日：2005-04-26

申请人： Ryuichi Sunayama ,  Aiichirou Inoue ,  Masaki Ukai

发明人： Ryuichi Sunayama ,  Aiichirou Inoue ,  Masaki Ukai

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/3804

摘要： An apparatus includes a branch instruction prediction unit configured to make branch prediction, and a branch prediction control unit configured to control an instruction fetch control unit, an instruction buffer, an instruction decoder, and the branch instruction prediction unit, wherein when the branch prediction control unit ascertains that the branch prediction by the branch instruction prediction unit is erroneous, the branch prediction control unit outputs to the instruction fetch control unit a signal for suppressing an instruction fetch request already supplied to the memory unit and outputs to the instruction buffer a signal for nullifying the instruction buffer during a period between a point in time at which the ascertainment is made by the branch prediction control unit that the branch prediction by the branch instruction prediction unit is erroneous and a point in time at which the instruction buffer fetches a correct instruction from the memory unit.

摘要翻译： 一种装置，包括：分支指示预测单元，用于进行分支预测;以及分支预测控制单元，被配置为控制指令获取控制单元，指令缓冲器，指令解码器和分支指令预测单元，其中当分支预测控制 单元确定分支指令预测单元的分支预测是错误的，分支预测控制单元向指令获取控制单元输出用于抑制已经提供给存储单元的指令获取请求的信号，并向指令缓冲器输出用于 在分支预测控制单元确定分支指令预测单元的分支预测错误的时间点和指令缓冲器获取正确指令的时间点之间的时间段期间使指令缓冲器无效 从存储单元。

公开(公告)号：US08601239B2

公开(公告)日：2013-12-03

申请号：US12827238

申请日：2010-06-30

申请人： Toshio Yoshida ,  Yasunobu Akizuki ,  Ryuichi Sunayama

发明人： Toshio Yoshida ,  Yasunobu Akizuki ,  Ryuichi Sunayama

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30101 ,  G06F9/30185

摘要： A processor includes a storage unit storing an instruction, an instruction extension information register that includes a first area and a second area, an instruction decoding unit that decodes a first prefix instruction including first extension information extending an immediately following instruction written to the first area when the first prefix instruction is executed, and that decodes a second prefix instruction including the first extension information and a second extension information extending an instruction immediately following two instructions of the second prefix instruction, an instruction packing unit that generates a packed instruction including at least one of the first prefix instruction or the second prefix instruction, and the instruction immediately following the first prefix instruction or the second prefix instruction when the instruction decoding unit decodes the first prefix instruction or the second prefix instruction, an instruction execution unit that executes the packed instruction generated by the instruction packing unit.

摘要翻译： 处理器包括存储指令的存储单元，包括第一区域和第二区域的指令扩展信息寄存器，指令解码单元，其对包含第一扩展信息的第一前缀指令进行解码，所述第一前缀指令包括第一扩展信息， 执行第一前缀指令，并且解码包括第一扩展信息的第二前缀指令和扩展紧跟在第二前缀指令的两个指令之后的指令的第二扩展信息;指令打包单元，其生成包括至少一个 第一前缀指令或第二前缀指令的指令，以及当指令解码单元解码第一前缀指令或第二前缀指令时紧跟在第一前缀指令或第二前缀指令之后的指令，执行指令执行单元， 剪切由指令包装单元生成的打包指令。

公开(公告)号：US20100095306A1

公开(公告)日：2010-04-15

申请号：US12638760

申请日：2009-12-15

申请人： Norihito GOMYO ,  Toshio Yoshida ,  Ryuichi Sunayama

发明人： Norihito GOMYO ,  Toshio Yoshida ,  Ryuichi Sunayama

IPC分类号： G06F9/46 ,  G06F9/44 ,  G06F11/00 ,  G06F9/302

CPC分类号： G06F9/3851 ,  G06F9/30083 ,  G06F9/3009 ,  G06F9/30189 ,  G06F9/3885

摘要： An arithmetic device simultaneously processes a plurality of threads and may continue the process by minimizing the degradation of the entire performance although a hardware error occurs. An arithmetic device 100 includes: an instruction execution circuit 101 capable of selectively executing a mode in which the instruction sequences of a plurality of threads are executed and a mode in which the instruction sequence of a single thread is executed; and a switch indication circuit 102 instructing the instruction execution circuit 101 to switch a thread mode.

摘要翻译： 算术装置同时处理多个线程，并且可以通过尽可能降低整个性能的劣化来继续该过程，尽管发生硬件错误。 算术装置100包括：指令执行电路101，其能够选择性地执行执行多个线程的指令序列的模式以及执行单线程的指令序列的模式; 和指示执行电路101切换线程模式的开关指示电路102。

公开(公告)号：US07603545B2

公开(公告)日：2009-10-13

申请号：US10345296

申请日：2003-01-16

申请人： Ryuichi Sunayama ,  Aiichiro Inoue

发明人： Ryuichi Sunayama ,  Aiichiro Inoue

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F9/3804 ,  G06F9/3842 ,  G06F9/3844

摘要： An instruction control method carries out an instruction in a processor to process instructions by out-of-order processing, using delay instructions for branching. The processor includes a storage unit, a branch predictor making branch predictions and a control unit which successively stores a plurality of delay instructions in the storage unit together with information indicating whether or not branch instructions corresponding to the delay instructions are predicted to branch by the branch predictor.

摘要翻译： 指令控制方法在处理器中执行指令，通过使用用于分支的延迟指令通过无序处理来处理指令。 该处理器包括一个存储单元，一个分支预测器进行分支预测和一个控制单元，该单元连同存储单元中的多个延迟指令一起连同指示是否预先分支了延迟指令的分支指令分支的信息 预测因子

公开(公告)号：US07412592B2

公开(公告)日：2008-08-12

申请号：US10994603

申请日：2004-11-23

申请人： Ryuichi Sunayama

发明人： Ryuichi Sunayama

IPC分类号： G06F9/315

CPC分类号： G06F9/3861 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3836

摘要： The branch instruction control apparatus of the present invention is a control apparatus in which a plurality of entries in which data required for the implementation control of the branch instructions is stored in order of decoding successively from the top entry, and said apparatus comprises a mechanism which, when one or more entries are successively released in order of older decoding from the top entry among the entries whose implementation control of the corresponding branch instruction has been completed, moves the contents of the remaining entries in a direction toward the top entry by the number of entries released, and a unit for storing data required for the implementation control of newly decoded branch instructions in one or more empty entries which are near the top entry including the entries which become empty by the movement, in the same cycle as in the movement of the said contents.

摘要翻译： 本发明的分支指令控制装置是一种控制装置，其中以从顶部条目连续解码的顺序存储分支指令的实现控制所需的数据的多个条目，并且所述装置包括： 当在对应的分支指令的实现控制已经完成的条目的条目中从先前条目顺序依次排列一个或多个条目时，将剩余条目的内容朝向顶部条目的方向移动数量 以及一个单元，用于存储在与移动相同的周期中的一个或多个空条目中的新解码的分支指令的实现控制所需的数据，所述空条目在包括由移动变空的条目的顶部条目附近 的内容。

公开(公告)号：US20100332800A1

公开(公告)日：2010-12-30

申请号：US12801871

申请日：2010-06-29

申请人： Ryuichi Sunayama

发明人： Ryuichi Sunayama

IPC分类号： G06F9/30 ,  G06F12/08 ,  G06F9/38

CPC分类号： G06F9/3804 ,  G06F9/3802 ,  G06F12/0859

摘要： An instruction control device connects to a cache memory that stores data frequently used among data stored in a main memory. The instruction control device includes: a first free-space determining unit that determines whether there is free space in an instruction buffer; a second free-space determining unit that manages an instruction fetch request queue that stores an instruction fetch data to be sent from the cache memory to the main memory, and determines whether a move-in buffer in the cache memory has free space for at least two entries if the first free-space determining unit determines that there is free space; and an instruction control unit that outputs an instruction prefetch request to the cache memory in accordance with an address boundary corresponding to a line size of the cache line, if the second free-space determining unit determines that the move-in buffer has free space.

摘要翻译： 指令控制装置连接到存储主存储器中存储的数据中经常使用的数据的高速缓冲存储器。 指令控制装置包括：第一自由空间确定单元，确定指令缓冲器中是否有空闲空间; 第二自由空间确定单元，其管理指令提取请求队列，所述指令获取请求队列存储要从所述高速缓冲存储器发送到所述主存储器的指令获取数据，并且确定所述高速缓冲存储器中的移入缓冲器是否具有至少自由空间 如果第一自由空间确定单元确定存在空闲空间，则两个条目; 以及指令控制单元，如果所述第二自由空间确定单元确定所述移入缓冲器具有可用空间，则根据与所述高速缓存行的行大小相对应的地址边界向所述高速缓存存储器输出指令预取请求。

公开(公告)号：US20100088544A1

公开(公告)日：2010-04-08

申请号：US12633840

申请日：2009-12-09

申请人： Norihito GOMYO ,  Ryuichi SUNAYAMA

发明人： Norihito GOMYO ,  Ryuichi SUNAYAMA

IPC分类号： G06F11/14

CPC分类号： G06F11/1405

摘要： A processor is provided that is capable of concurrently processing a sequence of instructions for a plurality of threads achieving the retry success rate equivalent to the success rate in processors that process a sequence of instructions for a single thread. An arithmetic device 200 is provided with an instruction execution circuit 201 for executing a plurality of threads, or an execution control circuit 202 for controlling the execution state or rerunning of the threads.

摘要翻译： 提供了一种处理器，其能够同时处理多个线程的指令序列，其实现与处理单个线程的指令序列的处理器中的成功率相当的重试成功率。 算术装置200具有用于执行多个线程的指令执行电路201，或者用于控制线程的执行状态或重新运行的执行控制电路202。

公开(公告)号：US20060026409A1

公开(公告)日：2006-02-02

申请号：US10994603

申请日：2004-11-23

申请人： Ryuichi Sunayama

发明人： Ryuichi Sunayama

IPC分类号： G06F9/44

CPC分类号： G06F9/3861 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3836

摘要： The branch instruction control apparatus of the present invention is a control apparatus in which a plurality of entries in which data required for the implementation control of the branch instructions is stored in order of decoding successively from the top entry, and said apparatus comprises a mechanism which, when one or more entries are successively released in order of older decoding from the top entry among the entries whose implementation control of the corresponding branch instruction has been completed, moves the contents of the remaining entries in a direction toward the top entry by the number of entries released, and a unit for storing data required for the implementation control of newly decoded branch instructions in one or more empty entries which are near the top entry including the entries which become empty by the movement, in the same cycle as in the movement of the said contents.

摘要翻译： 本发明的分支指令控制装置是一种控制装置，其中以从顶部条目连续解码的顺序存储分支指令的实现控制所需的数据的多个条目，并且所述装置包括： 当在对应的分支指令的实现控制已经完成的条目的条目中从先前条目顺序依次排列一个或多个条目时，将剩余条目的内容朝向顶部条目的方向移动数量 以及一个单元，用于存储在与移动相同的周期中的一个或多个空条目中的新解码的分支指令的实现控制所需的数据，所述空条目在包括由移动变空的条目的顶部条目附近 的内容。