公开(公告)号：US07765387B2

公开(公告)日：2010-07-27

申请号：US10352005

申请日：2003-01-28

申请人： Ryuichi Sunayama ,  Kuniki Morita ,  Aiichiro Inoue

发明人： Ryuichi Sunayama ,  Kuniki Morita ,  Aiichiro Inoue

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/321 ,  G06F9/3842 ,  G06F9/3844

摘要： A program counter control method controls instructions by an out-of-order method using a branch prediction mechanism and controls an architecture having delay instructions for branching. The method includes the steps of simultaneously committing a plurality of instructions including a branch instruction, when a branch prediction is successful and the branch instruction branches, and simultaneously updating a program counter and a next program counter depending on a number of committed instructions.

摘要翻译： 程序计数器控制方法通过使用分支预测机制的无序方法来控制指令，并且控制具有用于分支的延迟指令的架构。 该方法包括以下步骤：当分支预测成功并且分支指令分支时同时提交包括分支指令的多个指令，并且根据所提交的指令的数目同时更新程序计数器和下一个程序计数器。

公开(公告)号：US08060698B2

公开(公告)日：2011-11-15

申请号：US12219080

申请日：2008-07-15

申请人： Souta Kusachi ,  Kuniki Morita ,  Masaki Ukai ,  Tomoyuki Okawa

发明人： Souta Kusachi ,  Kuniki Morita ,  Masaki Ukai ,  Tomoyuki Okawa

IPC分类号： G06F12/00 ,  G06F12/16

CPC分类号： G06F12/0846 ,  G06F11/1064 ,  G06F12/0864

摘要： A cache controller controls at least one cache. The cache includes ways including a plurality of blocks that stores therein entry data. A writing unit writes degradation data to a failed block. The degradation data indicates that the failed block is in a degradation state. A reading unit reads entry data from a block. A determining unit determines, if the entry data obtained by the reading unit includes the degradation data, that the block is in the degradation state.

摘要翻译： 缓存控制器控制至少一个缓存。 缓存包括包括存储入口数据的多个块的方式。 写入单元将劣化数据写入故障块。 劣化数据表明故障块处于劣化状态。 读取单元从块读取条目数据。 确定单元确定由读取单元获得的输入数据是否包括劣化数据，判定该块处于退化状态。

公开(公告)号：US20080320327A1

公开(公告)日：2008-12-25

申请号：US12230242

申请日：2008-08-26

申请人： Tomoyuki OKAWA ,  Kuniki MORITA

发明人： Tomoyuki OKAWA ,  Kuniki MORITA

IPC分类号： G06F11/07

CPC分类号： G06F12/126 ,  G06F2212/1032

摘要： A degeneration control device that controls degeneration of a cache having a plurality of ways based on an error that occurs in response to an access request, includes a cache line degeneration information memory unit, which stores cache line degeneration information that indicates whether a cache line constituting each of the plurality of ways is degenerated, and a degeneration control unit, which writes, when an error that occurs in response to the access request causes a predetermined condition to be met, cache line degeneration information that indicates a predetermined cache line where the error occurs is degenerated in the cache line degeneration information memory unit.

摘要翻译： 一种退化控制装置，其基于响应于访问请求而发生的错误，控制具有多路的高速缓存的退化，包括高速缓存行退化信息存储单元，其存储高速缓存行退化信息，该高速缓存行退化信息指示构成 多个方法中的每一个都被退化，并且退化控制单元当响应于访问请求而发生的错误导致满足预定条件时，写入指示预定高速缓存行的高速缓存行退化信息，其中错误 发生在高速缓存行退化信息存储单元中退化。

公开(公告)号：US08006139B2

公开(公告)日：2011-08-23

申请号：US12230242

申请日：2008-08-26

申请人： Tomoyuki Okawa ,  Kuniki Morita

发明人： Tomoyuki Okawa ,  Kuniki Morita

IPC分类号： G06F11/00

CPC分类号： G06F12/126 ,  G06F2212/1032

摘要： A degeneration control device that controls degeneration of a cache having a plurality of ways based on an error that occurs in response to an access request, includes a cache line degeneration information memory unit, which stores cache line degeneration information that indicates whether a cache line constituting each of the plurality of ways is degenerated, and a degeneration control unit, which writes, when an error that occurs in response to the access request causes a predetermined condition to be met, cache line degeneration information that indicates a predetermined cache line where the error occurs is degenerated in the cache line degeneration information memory unit.

摘要翻译： 一种退化控制装置，其基于响应于访问请求而发生的错误，控制具有多路的高速缓存的退化，包括高速缓存行退化信息存储单元，其存储高速缓存行退化信息，该高速缓存行退化信息指示构成 多个方法中的每一个都被退化，并且退化控制单元当响应于访问请求而发生的错误导致满足预定条件时，写入指示预定高速缓存行的高速缓存行退化信息，其中错误 发生在高速缓存行退化信息存储单元中退化。

公开(公告)号：US20080282037A1

公开(公告)日：2008-11-13

申请号：US12219080

申请日：2008-07-15

申请人： Souta Kusachi ,  Kuniki Morita ,  Masaki Ukai ,  Tomoyuki Okawa

发明人： Souta Kusachi ,  Kuniki Morita ,  Masaki Ukai ,  Tomoyuki Okawa

IPC分类号： G06F12/00

CPC分类号： G06F12/0846 ,  G06F11/1064 ,  G06F12/0864

摘要： A cache controller controls at least one cache. The cache includes ways including a plurality of blocks that stores therein entry data. A writing unit writes degradation data to a failed block. The degradation data indicates that the failed block is in a degradation state. A reading unit reads entry data from a block. A determining unit determines, if the entry data obtained by the reading unit includes the degradation data, that the block is in the degradation state.

摘要翻译： 缓存控制器控制至少一个缓存。 缓存包括包括存储入口数据的多个块的方式。 写入单元将劣化数据写入故障块。 劣化数据表明故障块处于劣化状态。 读取单元从块读取条目数据。 确定单元确定由读取单元获得的输入数据是否包括劣化数据，判定该块处于退化状态。

公开(公告)号：US4735403A

公开(公告)日：1988-04-05

申请号：US9041

申请日：1987-01-28

申请人： Yukio Matsumoto ,  Noriyuki Saito ,  Kuniki Morita

发明人： Yukio Matsumoto ,  Noriyuki Saito ,  Kuniki Morita

IPC分类号： F16F1/06 ,  F16F1/04

CPC分类号： F16F1/042

摘要： It is known that a sectional shape of a spring wire can be formed into an oval made by a semicircle and a semiellipse. However, it has been found that such a shape is not the best obtainable, and that stress distribution can be improved by increasing the diameter of the spring wire slightly in a portion where the stress is greatest, along the semielliptical surface. Parameters are disclosed for determining dimensions that result in increased energy efficiency.

摘要翻译： 已知弹簧丝线的截面形状可以形成为由半圆形和半椭圆形形成的椭圆形。 然而，已经发现这种形状不是最好的，并且通过沿着半椭圆表面在应力最大的部分稍微增加弹簧丝的直径可以提高应力分布。 公开了用于确定导致能量效率提高的尺寸的参数。

公开(公告)号：US20120246408A1

公开(公告)日：2012-09-27

申请号：US13359605

申请日：2012-01-27

申请人： Shuji YAMAMURA ,  Kuniki Morita

发明人： Shuji YAMAMURA ,  Kuniki Morita

IPC分类号： G06F12/08

CPC分类号： G06F12/0895 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/128 ,  G06F2212/6082

摘要： A physical process ID (PPID) is stored for each cache block of each set, and a MAX WAY number for each PPID value is stored for each of index values #1 to #n. A MAX WAY number corresponding to a certain PPID value in a certain index value indicates the maximum number of cache blocks having the PPID value, which can be stored in the index value. The number of ways at the time of a cache miss is controlled not to exceed the MAX WAY number of each PPID value for each index value.

摘要翻译： 为每组的每个高速缓存块存储物理进程ID（PPID），并为每个索引值＃1至#n存储每个PPID值的MAX WAY号。 对应于特定索引值中的某个PPID值的MAX WAY号表示具有PPID值的高速缓存块的最大数量，其可以存储在索引值中。 控制缓存未命中时的方式数量不超过每个索引值的每个PPID值的MAX WAY数。

公开(公告)号：US4953835A

公开(公告)日：1990-09-04

申请号：US378678

申请日：1989-07-12

申请人： Yukio Matsumoto ,  Horiyuki Saito ,  Kuniki Morita

发明人： Yukio Matsumoto ,  Horiyuki Saito ,  Kuniki Morita

IPC分类号： F16F1/06 ,  F16F1/04

CPC分类号： F16F1/042

摘要： Wire of an oval type cross sectional shape having a surface formed of a semicircle and semiellipse tangent to each other has been used for coiled springs. Stress distribution in wire of such a shape can be improved by increasing the dimension of the spring wire in a direction perpendicular to the axis of the spring. One such cross sectional shape is formed by semicircle and semiellipse portions connected by straight lines.