公开(公告)号：US20230318658A1

公开(公告)日：2023-10-05

申请号：US18174236

申请日：2023-02-24

Applicant: STMICROELECTRONICS SA ,  STIMICROELECTRONICS (GRENOBLE) SAS

Inventor： Gregoire Montjaux ,  Marc Houdebine

IPC: H04B5/00 ,  H04L7/033 ,  H03L7/099

CPC classification number: H04B5/0031 ,  H03L7/0992 ,  H03L7/0994 ,  H04L7/033

Abstract: A device is configured to receive a first carrier signal, and deliver a second carrier signal, and has a phase-locked loop including a first domain including an oscillator configured to generate a signal at a given frequency, and a circuit configured to generate information representative of the frequency of the signal generated by the oscillator, and to generate the second carrier signal and a clock signal, the first domain being clocked by the first carrier signal, a second domain, clocked by the clock signal, including a circuit configured to compare the frequency of the signal generated by the oscillator with the frequency of the first carrier signal and to control the oscillator, a matching circuit configured to transfer information representative of the frequency of the signal generated by the oscillator from the first domain to the second domain.