Systems and methods for built in self test jitter measurement
    1.
    发明授权
    Systems and methods for built in self test jitter measurement 失效
    内置自检抖动测量的系统和方法

    公开(公告)号:US08283933B2

    公开(公告)日:2012-10-09

    申请号:US12707534

    申请日:2010-02-17

    CPC classification number: G01R29/26 G01R31/31709 H04L1/205

    Abstract: An apparatus configured for built in self test (BIST) jitter measurement is described. The apparatus includes a time-to-voltage converter. The time-to-voltage converter generates a voltage signal proportional to timing jitter present in a clock/data signal input. The apparatus also includes feedback circuitry for the time-to-voltage converter. The feedback circuitry provides a ramp slope for the time-to-voltage converter. The apparatus further includes a calibration controller. The calibration controller provides control signals to the time-to-voltage converter for process-independent calibration. The apparatus also includes a sample-and-hold (S/H) circuit. The S/H circuit provides a set bias voltage to the time-to-voltage converter once calibration is complete.

    Abstract translation: 描述了内置自测(BIST)抖动测量的装置。 该装置包括时间 - 电压转换器。 时间到电压转换器产生与时钟/数据信号输入中存在的定时抖动成比例的电压信号。 该装置还包括用于时间 - 电压转换器的反馈电路。 反馈电路为时间到电压转换器提供斜坡斜率。 该装置还包括校准控制器。 校准控制器为时间到电压转换器提供控制信号,用于与过程无关的校准。 该装置还包括采样保持(S / H)电路。 校准完成后,S / H电路为时间到电压转换器提供设定的偏置电压。

    Systems and methods for vector-based analog-to-digital converter sequential testing
    2.
    发明授权
    Systems and methods for vector-based analog-to-digital converter sequential testing 失效
    基于矢量的模数转换器顺序测试的系统和方法

    公开(公告)号:US08310385B2

    公开(公告)日:2012-11-13

    申请号:US12777091

    申请日:2010-05-10

    CPC classification number: H03M1/1095 H03M1/12

    Abstract: A method for providing built-in self test (BiST) for an analog-to-digital converter (ADC) by automatic test equipment (ATE) is described. Output codes are received from the ADC. The output codes are translated to generate a functional pattern. Performance metrics are determined for the ADC using the functional pattern. The ADC may be on a device-under-test (DUT).

    Abstract translation: 描述了通过自动测试设备(ATE)为模数转换器(ADC)提供内置自检(BiST)的方法。 从ADC接收输出代码。 转换输出代码以生成功能模式。 使用功能模式为ADC确定性能指标。 ADC可能在被测器件(DUT)上。

    SYSTEMS AND METHODS FOR A PHASE LOCKED LOOP BUILT IN SELF TEST
    3.
    发明申请
    SYSTEMS AND METHODS FOR A PHASE LOCKED LOOP BUILT IN SELF TEST 审中-公开
    在自检中建立相位锁定环路的系统和方法

    公开(公告)号:US20100293426A1

    公开(公告)日:2010-11-18

    申请号:US12762985

    申请日:2010-04-19

    CPC classification number: G01R31/31709

    Abstract: An apparatus configured for a phase locked loop (PLL) built in self test (BIST) jitter measurement is described. The apparatus includes a phase detector. The phase detector produces a digital signal that describes a comparison between a reference signal and a feedback signal. The apparatus also includes a BIST controller. The BIST controller accumulates the digital signal with successive digital signals. The apparatus also includes a communication pin. The communication pin sends the accumulated signal to automatic test equipment (ATE) that determines whether the PLL is operating correctly based on the accumulated signal.

    Abstract translation: 描述了一种配置用于内置自测(BIST)抖动测量的锁相环(PLL)的装置。 该装置包括相位检测器。 相位检测器产生描述参考信号和反馈信号之间的比较的数字信号。 该装置还包括BIST控制器。 BIST控制器用连续的数字信号累加数字信号。 该装置还包括通信引脚。 通信引脚将累积信号发送到自动测试设备(ATE),根据累加信号确定PLL是否正常工作。

    METHODS AND APPARATUS FOR BUILT IN SELF TEST OF ANALOG-TO-DIGITAL CONVERTORS
    4.
    发明申请
    METHODS AND APPARATUS FOR BUILT IN SELF TEST OF ANALOG-TO-DIGITAL CONVERTORS 有权
    在模拟数字转换器自检中建立的方法和设备

    公开(公告)号:US20100253559A1

    公开(公告)日:2010-10-07

    申请号:US12697435

    申请日:2010-02-01

    CPC classification number: H03K4/501 H03K4/90 H03M1/109 H03M1/12

    Abstract: An apparatus configured for built in self test (BiST) of analog-to-digital convertors (ADCs) is described. The apparatus includes an ADC to be tested. The apparatus includes a ramp generator. The ramp generator provides a voltage ramp to the ADC. The apparatus further includes feedback circuitry for the ramp generator. The feedback circuitry maintains a constant ramp slope for the ramp generator. The apparatus includes an interval counter. The interval counter provides a timing reference.

    Abstract translation: 描述了配置用于模数转换器(ADC)的内置自检(BiST)的装置。 该装置包括要测试的ADC。 该装置包括斜坡发生器。 斜坡发生器为ADC提供电压斜坡。 该装置还包括用于斜坡发生器的反馈电路。 反馈电路为斜坡发生器保持恒定的斜坡斜率。 该装置包括间隔计数器。 间隔计数器提供定时参考。

    Real-time adaptive hybrid BiST solution for low-cost and low-resource ate production testing of analog-to-digital converters
    5.
    发明授权
    Real-time adaptive hybrid BiST solution for low-cost and low-resource ate production testing of analog-to-digital converters 失效
    实时自适应混合BiST解决方案,用于模拟 - 数字转换器的低成本和低资源生产测试

    公开(公告)号:US08510073B2

    公开(公告)日:2013-08-13

    申请号:US12957277

    申请日:2010-11-30

    CPC classification number: H03M1/109 H03M1/12

    Abstract: An integrated circuit configured to perform hybrid built in self test (BiST) of analog-to-digital converters (ADCs) is described. The integrated circuit includes an ADC. The integrated circuit also includes a BiST controller that controls the hybrid BiST. The integrated circuit further includes a ramp generator that provides a voltage ramp to the ADC. The integrated circuit also includes a first multiplexer that switches an input for the ADC between the voltage ramp and a voltage reference signal. The integrated circuit further includes feedback circuitry for the ramp generator that maintains a constant ramp slope for the ramp generator. The integrated circuit also includes an interval counter that provides a timing reference.

    Abstract translation: 描述了被配置为执行模数转换器(ADC)的混合内置自测(BiST)的集成电路。 集成电路包括一个ADC。 集成电路还包括控制混合BiST的BiST控制器。 集成电路还包括向ADC提供电压斜坡的斜坡发生器。 集成电路还包括第一多路复用器,其在电压斜坡和电压参考信号之间切换ADC的输入。 集成电路还包括用于斜坡发生器的反馈电路,其为斜坡发生器保持恒定的斜坡斜率。 集成电路还包括提供定时参考的间隔计数器。

    Methods and apparatus for built in self test of analog-to-digital convertors
    6.
    发明授权
    Methods and apparatus for built in self test of analog-to-digital convertors 有权
    模拟数字转换器内置自检的方法和装置

    公开(公告)号:US08106801B2

    公开(公告)日:2012-01-31

    申请号:US12697435

    申请日:2010-02-01

    CPC classification number: H03K4/501 H03K4/90 H03M1/109 H03M1/12

    Abstract: An apparatus configured for built in self test (BiST) of analog-to-digital convertors (ADCs) is described. The apparatus includes an ADC to be tested. The apparatus includes a ramp generator. The ramp generator provides a voltage ramp to the ADC. The apparatus further includes feedback circuitry for the ramp generator. The feedback circuitry maintains a constant ramp slope for the ramp generator. The apparatus includes an interval counter. The interval counter provides a timing reference.

    Abstract translation: 描述了配置用于模数转换器(ADC)的内置自检(BiST)的装置。 该装置包括要测试的ADC。 该装置包括斜坡发生器。 斜坡发生器为ADC提供电压斜坡。 该装置还包括用于斜坡发生器的反馈电路。 反馈电路为斜坡发生器保持恒定的斜坡斜率。 该装置包括间隔计数器。 间隔计数器提供定时参考。

    REAL-TIME ADAPTIVE HYBRID BiST SOLUTION FOR LOW-COST AND LOW-RESOURCE ATE PRODUCTION TESTING OF ANALOG-TO-DIGITAL CONVERTERS
    7.
    发明申请
    REAL-TIME ADAPTIVE HYBRID BiST SOLUTION FOR LOW-COST AND LOW-RESOURCE ATE PRODUCTION TESTING OF ANALOG-TO-DIGITAL CONVERTERS 失效
    实时自适应混合BiST解决方案,用于模拟数字转换器的低成本和低资源优化生产测试

    公开(公告)号:US20110137604A1

    公开(公告)日:2011-06-09

    申请号:US12957277

    申请日:2010-11-30

    CPC classification number: H03M1/109 H03M1/12

    Abstract: An integrated circuit configured to perform hybrid built in self test (BiST) of analog-to-digital converters (ADCs) is described. The integrated circuit includes an ADC. The integrated circuit also includes a BiST controller that controls the hybrid BiST. The integrated circuit further includes a ramp generator that provides a voltage ramp to the ADC. The integrated circuit also includes a first multiplexer that switches an input for the ADC between the voltage ramp and a voltage reference signal. The integrated circuit further includes feedback circuitry for the ramp generator that maintains a constant ramp slope for the ramp generator. The integrated circuit also includes an interval counter that provides a timing reference.

    Abstract translation: 描述了被配置为执行模数转换器(ADC)的混合内置自测(BiST)的集成电路。 集成电路包括一个ADC。 集成电路还包括控制混合BiST的BiST控制器。 集成电路还包括向ADC提供电压斜坡的斜坡发生器。 集成电路还包括第一多路复用器,其在电压斜坡和电压参考信号之间切换ADC的输入。 集成电路还包括用于斜坡发生器的反馈电路,其为斜坡发生器保持恒定的斜坡斜率。 集成电路还包括提供定时参考的间隔计数器。

    SYSTEMS AND METHODS FOR VECTOR-BASED ANALOG-TO-DIGITAL CONVERTER SEQUENTIAL TESTING
    8.
    发明申请
    SYSTEMS AND METHODS FOR VECTOR-BASED ANALOG-TO-DIGITAL CONVERTER SEQUENTIAL TESTING 失效
    用于基于矢量的模拟数字转换器顺序测试的系统和方法

    公开(公告)号:US20100289679A1

    公开(公告)日:2010-11-18

    申请号:US12777091

    申请日:2010-05-10

    CPC classification number: H03M1/1095 H03M1/12

    Abstract: A method for providing built-in self test (BiST) for an analog-to-digital converter (ADC) by automatic test equipment (ATE) is described. Output codes are received from the ADC. The output codes are translated to generate a functional pattern. Performance metrics are determined for the ADC using the functional pattern. The ADC may be on a device-under-test (DUT).

    Abstract translation: 描述了通过自动测试设备(ATE)为模数转换器(ADC)提供内置自检(BiST)的方法。 从ADC接收输出代码。 转换输出代码以生成功能模式。 使用功能模式为ADC确定性能指标。 ADC可能在被测器件(DUT)上。

    SYSTEMS AND METHODS FOR BUILT IN SELF TEST JITTER MEASUREMENT
    9.
    发明申请
    SYSTEMS AND METHODS FOR BUILT IN SELF TEST JITTER MEASUREMENT 失效
    用于建立自检测试仪测量的系统和方法

    公开(公告)号:US20100231233A1

    公开(公告)日:2010-09-16

    申请号:US12707534

    申请日:2010-02-17

    CPC classification number: G01R29/26 G01R31/31709 H04L1/205

    Abstract: An apparatus configured for built in self test (BIST) jitter measurement is described. The apparatus includes a time-to-voltage converter. The time-to-voltage converter generates a voltage signal proportional to timing jitter present in a clock/data signal input. The apparatus also includes feedback circuitry for the time-to-voltage converter. The feedback circuitry provides a ramp slope for the time-to-voltage converter. The apparatus further includes a calibration controller. The calibration controller provides control signals to the time-to-voltage converter for process-independent calibration. The apparatus also includes a sample-and-hold (S/H) circuit. The S/H circuit provides a set bias voltage to the time-to-voltage converter once calibration is complete.

    Abstract translation: 描述了内置自测(BIST)抖动测量的装置。 该装置包括时间 - 电压转换器。 时间到电压转换器产生与时钟/数据信号输入中存在的定时抖动成比例的电压信号。 该装置还包括用于时间 - 电压转换器的反馈电路。 反馈电路为时间到电压转换器提供斜坡斜率。 该装置还包括校准控制器。 校准控制器为时间到电压转换器提供控制信号,用于与过程无关的校准。 该装置还包括采样保持(S / H)电路。 校准完成后,S / H电路为时间到电压转换器提供设定的偏置电压。

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