System and method for testing multiple processor modes for processor design verification and validation
    1.
    发明授权
    System and method for testing multiple processor modes for processor design verification and validation 有权
    用于测试多种处理器模式以进行处理器设计验证和验证的系统和方法

    公开(公告)号:US08006221B2

    公开(公告)日:2011-08-23

    申请号:US11853170

    申请日:2007-09-11

    IPC分类号: G06F17/50

    CPC分类号: G06F11/263

    摘要: A system and method for generating a test case and a bit mask that allows a test case executor the ability to re-execute the test case multiple times using different machine state register bit sets. A test case generator creates a bit mask based upon identified invariant bits and semi-invariant bits. The test case generator includes compensation values corresponding to the semi-invariant bits into a test case, and provides the test case, along with the bit mask, to a test case executor. In turn, the test case executor dispatches the test case multiple times, each time with a different machine state register bit set, to a processor. Each of the machine state register bit sets places the processor in different modes.

    摘要翻译: 用于生成测试用例和位掩码的系统和方法,允许测试用例执行器使用不同的机器状态寄存器位集多次重新执行测试用例。 测试用例发生器基于识别的不变位和半不变位创建位掩码。 测试用例发生器包括与半不变位相对应的补偿值到测试用例中,并将测试用例以及位掩码提供给测试用例执行器。 反过来,测试用例执行器将每个测试用例分配到不同的机器状态寄存器位设置的多个处理器。 每个机器状态寄存器位组将处理器置于不同的模式。

    System and Method for Testing Multiple Processor Modes for Processor Design Verification and Validation
    2.
    发明申请
    System and Method for Testing Multiple Processor Modes for Processor Design Verification and Validation 有权
    用于测试处理器设计验证和验证的多处理器模式的系统和方法

    公开(公告)号:US20090070629A1

    公开(公告)日:2009-03-12

    申请号:US11853170

    申请日:2007-09-11

    IPC分类号: G06F11/263

    CPC分类号: G06F11/263

    摘要: A system and method for generating a test case and a bit mask that allows a test case executor the ability to re-execute the test case multiple times using different machine state register bit sets. A test case generator creates a bit mask based upon identified invariant bits and semi-invariant bits. The test case generator includes compensation values corresponding to the semi-invariant bits into a test case, and provides the test case, along with the bit mask, to a test case executor. In turn, the test case executor dispatches the test case multiple times, each time with a different machine state register bit set, to a processor. Each of the machine state register bit sets places the processor in different modes.

    摘要翻译: 用于生成测试用例和位掩码的系统和方法,允许测试用例执行器使用不同的机器状态寄存器位集多次重新执行测试用例。 测试用例发生器基于识别的不变位和半不变位创建位掩码。 测试用例生成器包括与半不变位对应的补偿值到测试用例中,并将测试用例以及位掩码提供给测试用例执行器。 反过来,测试用例执行器将每个测试用例分配到不同的机器状态寄存器位设置的多个处理器。 每个机器状态寄存器位组将处理器置于不同的模式。