公开(公告)号：US20090281781A1

公开(公告)日：2009-11-12

申请号：US12115977

申请日：2008-05-06

申请人： Ronald D. Rose ,  Sanjay Upreti

发明人： Ronald D. Rose ,  Sanjay Upreti

IPC分类号： G06F9/455

CPC分类号： G06F17/5036 ,  G06F11/261

摘要： A method, apparatus and program product are provided for performing a noise, timing, or other signal integrity simulation of a circuit under test. A simulation cache structure is accessed to retrieve cached simulation results for a first portion of the circuit under test. Simulation is performed on a second portion of the circuit under test to generate simulation results for the second portion. Simulation results are generated for the circuit under test by combining the simulation results for the second portion with the cached simulation results for the first portion.

摘要翻译： 提供了一种用于对被测电路进行噪声，定时或其他信号完整性仿真的方法，装置和程序产品。 访问模拟缓存结构以检索被测电路的第一部分的缓存仿真结果。 在被测电路的第二部分进行仿真以产生第二部分的仿真结果。 通过将第二部分的模拟结果与第一部分的缓存模拟结果相结合，为被测电路生成仿真结果。

公开(公告)号：US06175947B1

公开(公告)日：2001-01-16

申请号：US09062853

申请日：1998-04-20

申请人： Saila Ponnapalli ,  Timothy Lehner ,  Sanjay Upreti

发明人： Saila Ponnapalli ,  Timothy Lehner ,  Sanjay Upreti

IPC分类号： G06F1716

CPC分类号： G06F17/5036

摘要： A method for accurately extracting capacitance and inductance parasitics from an electrical network representing a three-dimensional wiring of an integrated circuit chip or module is described. The extraction process can be performed either prior to or after completing a detailed wiring of the chip. In the former case, the method utilizes congestion information and approximate wiring length data to estimate the probability of encountering a particular pattern and the most accurate estimated capacitance which can arrived at. In the latter case, the wiring is partitioned into three-dimensional recognizable patterns, and a database of precomputed parasitics for each pattern is queried in order to obtain highly accurate parasitics within a limited number of machine cycles. The number of patterns is assumed to be sufficiently small to be memory and time efficient and to be arrived at in real-time.

摘要翻译： 描述了一种从表示集成电路芯片或模块的三维布线的电网精确地提取电容和电感寄生效应的方法。 提取过程可以在完成芯片的详细布线之前或之后进行。 在前一种情况下，该方法利用拥塞信息和近似布线长度数据来估计遇到特定模式的概率和可以达到的最准确的估计电容。 在后一种情况下，布线被划分成三维可识别的图案，并且查询每个图案的预计算寄生效应的数据库，以便在有限数量的机器周期内获得高精度的寄生效应。 模式的数量被假定为足够小以便成为记忆和时间有效的并且被实时地实现。

公开(公告)号：US07533357B2

公开(公告)日：2009-05-12

申请号：US11421863

申请日：2006-06-02

申请人： Kurt A. Carlsen ,  Amol A. Joshi ,  Faraydon Pakbaz ,  Sanjay Upreti

发明人： Kurt A. Carlsen ,  Amol A. Joshi ,  Faraydon Pakbaz ,  Sanjay Upreti

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of estimating decaps required for an IC during an initial floorplanning design phase begins by obtaining voltage variation waveforms for a plurality of nodes in a power distribution network of the IC. Next, the method computes a minimum value for each of the voltage variation waveforms and selects voltage variation waveforms below a minimum threshold value. Following this, an FDA is performed on the voltage variation waveforms below the minimum threshold value to create a set of frequency values. This involves performing an FFT on each of the voltage variation waveforms to obtain frequency domain data, wherein frequencies that cause a drop in voltage in the plurality of nodes are filtered. The method then sorts the frequency domain data, wherein the frequency domain data is arranged in order based on amplitude value, total power, frequency components, and/or amplitude of imaginary components.

摘要翻译： 在初始布局规划设计阶段期间估计IC所需的分解的方法通过获得IC的配电网络中的多个节点的电压变化波形开始。 接下来，该方法计算每个电压变化波形的最小值，并选择低于最小阈值的电压变化波形。 此后，对低于最小阈值的电压变化波形执行FDA，以创建一组频率值。 这涉及对每个电压变化波形执行FFT以获得频域数据，其中导致多个节点中的电压下降的频率被滤波。 该方法然后对频域数据进行排序，其中基于振幅值，总功率，频率分量和/或虚部的振幅来顺序地布置频域数据。

公开(公告)号：US20070283299A1

公开(公告)日：2007-12-06

申请号：US11421863

申请日：2006-06-02

申请人： Kurt A Carlsen ,  Amol A. Joshi ,  Faraydon Pakbaz ,  Sanjay Upreti

发明人： Kurt A Carlsen ,  Amol A. Joshi ,  Faraydon Pakbaz ,  Sanjay Upreti

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of estimating decaps required for an IC during an initial floorplanning design phase begins by obtaining voltage variation waveforms for a plurality of nodes in a power distribution network of the IC. Next, the method computes a minimum value for each of the voltage variation waveforms and selects voltage variation waveforms below a minimum threshold value. Following this, an FDA is performed on the voltage variation waveforms below the minimum threshold value to create a set of frequency values. This involves performing an FFT on each of the voltage variation waveforms to obtain frequency domain data, wherein frequencies that cause a drop in voltage in the plurality of nodes are filtered. The method then sorts the frequency domain data, wherein the frequency domain data is arranged in order based on amplitude value, total power, frequency components, and/or amplitude of imaginary components.

摘要翻译： 在初始布局规划设计阶段期间估计IC所需的分解的方法通过获得IC的配电网络中的多个节点的电压变化波形开始。 接下来，该方法计算每个电压变化波形的最小值，并选择低于最小阈值的电压变化波形。 此后，对低于最小阈值的电压变化波形执行FDA，以创建一组频率值。 这涉及对每个电压变化波形执行FFT以获得频域数据，其中导致多个节点中的电压下降的频率被滤波。 该方法然后对频域数据进行排序，其中基于振幅值，总功率，频率分量和/或虚部的振幅来顺序地布置频域数据。

公开(公告)号：US20090281750A1

公开(公告)日：2009-11-12

申请号：US12116248

申请日：2008-05-07

申请人： Anita Natarajan ,  Ronald D. Rose ,  Sanjay Upreti

发明人： Anita Natarajan ,  Ronald D. Rose ,  Sanjay Upreti

IPC分类号： G01R29/26

CPC分类号： G06F17/5036

摘要： Method and apparatus for improving performance of noise analysis using a threshold based combination of noise estimation and simulation. The method includes classifying a circuit into one of four defined groups, determining if an input noise is small enough to skip simulation, estimating an output noise wave, scaling down a generated wave by a scaling factor depending on the circuit type, and determining if the estimated output noise is small enough to propagate or instead requires simulation.

摘要翻译： 使用基于阈值的噪声估计和模拟组合来提高噪声分析性能的方法和装置。 该方法包括将电路分为四个定义的组之一，确定输入噪声是否足够小以跳过仿真，估计输出噪声波，根据电路类型按比例缩放所生成的波，并确定是否 估计的输出噪声足够小以传播或需要仿真。

公开(公告)号：US07143014B2

公开(公告)日：2006-11-28

申请号：US10132101

申请日：2002-04-25

申请人： Sanjay Upreti

发明人： Sanjay Upreti

IPC分类号： G06F17/10 ,  G06F17/50

CPC分类号： G06F17/5036

摘要： A system and method is described for the simulation of the transfer function of very large RC networks of IC chips, such as VLSI. Both the real and imaginary components of the transfer function of RC networks have a property of changing more rapidly at lower frequencies but changing less rapidly at higher frequencies. Methods are employed which interpolate between transfer functions of the RC network for specific frequencies in order to derive an interpolated transfer function of the RC network.

公开(公告)号：US08438001B2

公开(公告)日：2013-05-07

申请号：US12116248

申请日：2008-05-07

申请人： Anita Natarajan ,  Ronald D. Rose ,  Sanjay Upreti

发明人： Anita Natarajan ,  Ronald D. Rose ,  Sanjay Upreti

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Method and apparatus for improving performance of noise analysis using a threshold based combination of noise estimation and simulation. The method includes classifying a circuit into one of four defined groups, determining if an input noise is small enough to skip simulation, estimating an output noise wave, scaling down a generated wave by a scaling factor depending on the circuit type, and determining if the estimated output noise is small enough to propagate or instead requires simulation.

摘要翻译： 使用基于阈值的噪声估计和模拟组合来提高噪声分析性能的方法和装置。 该方法包括将电路分为四个定义的组之一，确定输入噪声是否足够小以跳过仿真，估计输出噪声波，根据电路类型按比例缩放所生成的波，并确定是否 估计的输出噪声足够小以传播或需要仿真。