公开(公告)号：US5574923A

公开(公告)日：1996-11-12

申请号：US59543

申请日：1993-05-10

申请人： Jay Heeb ,  Sunil Shenoy ,  Scott Huck

发明人： Jay Heeb ,  Sunil Shenoy ,  Scott Huck

IPC分类号： G06F7/76 ,  G06F9/34 ,  G06F12/08 ,  G06F13/40 ,  G06F13/38 ,  G06F7/00 ,  G06F12/04

CPC分类号： G06F7/768 ,  G06F12/0802 ,  G06F13/4013 ,  G06F9/34

摘要： A method and apparatus for performing bi-endian byte and short accesses in a single endian microprocessor. The present invention is used in a microprocessor or in a microprocessor in a computer system. The present invention provides a single endian microprocessor that promotes sub-word accesses to word accesses with a means for manipulating the two least significant bits of the access address to point to the correct sub-word data returned during an access to bi-endian external memory. The method for manipulating the address bits is also used to allow a single endian data cache to operate with the bi-endian external memory. The two LSBs of the address are manipulated such that the pointer values are A1# and A0# for word promoted byte accesses or cacheable accesses. For word promoted short accesses or cacheable accesses, the pointer values are A1# and A0. The present invention offers increased flexibility in interfacing a single-endian microprocessor with bi-endian systems. The present invention provides easy interfacing without undue or overly complex modifications to existing circuits.

摘要翻译： 一种用于在单端微处理器中执行双端字节和短接入的方法和装置。 本发明用于计算机系统中的微处理器或微处理器。 本发明提供了一种单端微处理器，其利用用于操纵访问地址的两个最低有效位的装置来指向在访问双端外部存储器期间返回的正确子字数据的单字访问到字访问 。 用于操纵地址位的方法也用于允许单端数据高速缓存与双端外部存储器一起操作。 地址的两个LSB被操纵，使得指针值是用于字提升字节访问或可缓存访问的A1＃和A0＃。 对于字提升的短访问或可缓存访问，指针值为A1＃和A0。 本发明提供了将单端微处理器与双端系统连接的增加的灵活性。 本发明提供了容易的接口，而没有对现有电路进行过度或过度复杂的修改。

公开(公告)号：US5313605A

公开(公告)日：1994-05-17

申请号：US630534

申请日：1990-12-20

申请人： Scott Huck ,  Sunil Shenoy ,  Frank S. Smith

发明人： Scott Huck ,  Sunil Shenoy ,  Frank S. Smith

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/00 ,  G06F15/78 ,  G11C15/00

CPC分类号： G06F12/0886 ,  G06F12/0802

摘要： A hierarchical memory which includes a backing store read/write memory (18) for storing first words, and a read-only memory RAM (60) for storing frequently used words. The buffer store has two parts, a cache RAM (64) and a two-word queue (62) comprised of two fetch buffers. The cache RAM is provided for storing a copy of some of the word stored in the backing store in accordance with a use algorithm. The ROM, queue buffers and cache RAM are simultaneously searched to see if the address for requested words is in either of them. If not, a fetch (76) is made of the backing store (18) and the words are written into the fetch buffers. The next time that address is presented, the fetch buffers are written into the cache and simultaneously read out to the bus. A first Y-mux (63) is provided between the ROM and the cache RAM for multiplexing the appropriate ROM columns to drive the Cache RAM bit lines directly when an internal micro-address is selected. The word positions within a row of the ROM are so ordered as to enable multiple words to be read out simultaneously regardless of what starting address is presented to the ROM. A second Y-mux (67) is provided between the cache RAM and the bus (19) for multiplexing the multiple words. The second Y-mux is controlled by at least one bit of the internally selected address. A multiplexer (74) is connected to the second Y-mux for shifting its input an appropriate amount according to bits of the starting address, such that the correct words are read out in the correct position.

摘要翻译： 分层存储器，其包括用于存储第一字的后备存储读/写存储器（18）和用于存储频繁使用的字的只读存储器RAM（60）。 缓冲存储器具有两个部分，一个高速缓存RAM（64）和一个由两个读取缓冲器组成的双字队列（62）。 缓存RAM被提供用于根据使用算法存储存储在后备存储器中的一些字的副本。 同时搜索ROM，队列缓冲区和高速缓存RAM，查看请求的字的地址是否在其中。 如果不是，则由后备存储器（18）提取（76），并将这些字写入读取缓冲器。 下一次该地址被呈现时，获取缓冲区被写入高速缓存并同时读出到总线。 在ROM和高速缓冲存储器RAM之间提供第一Y多路复用器（63），用于多路复用适当的ROM列以在选择内部微地址时直接驱动Cache RAM位线。 ROM的一行内的单词位置如此排序，以便能够同时读出多个单词，而不管哪个起始地址被呈现给ROM。 在高速缓冲存储器RAM和总线（19）之间提供第二Y多路复用器（67），用于复用多个字。 第二个Y-MUX由内部选择的地址的至少一位控制。 多路复用器（74）连接到第二Y-多路复用器，用于根据起始地址的位将其输入移位适当的量，使得在正确位置读出正确的字。