公开(公告)号：US5574923A

公开(公告)日：1996-11-12

申请号：US59543

申请日：1993-05-10

申请人： Jay Heeb ,  Sunil Shenoy ,  Scott Huck

发明人： Jay Heeb ,  Sunil Shenoy ,  Scott Huck

IPC分类号： G06F7/76 ,  G06F9/34 ,  G06F12/08 ,  G06F13/40 ,  G06F13/38 ,  G06F7/00 ,  G06F12/04

CPC分类号： G06F7/768 ,  G06F12/0802 ,  G06F13/4013 ,  G06F9/34

摘要： A method and apparatus for performing bi-endian byte and short accesses in a single endian microprocessor. The present invention is used in a microprocessor or in a microprocessor in a computer system. The present invention provides a single endian microprocessor that promotes sub-word accesses to word accesses with a means for manipulating the two least significant bits of the access address to point to the correct sub-word data returned during an access to bi-endian external memory. The method for manipulating the address bits is also used to allow a single endian data cache to operate with the bi-endian external memory. The two LSBs of the address are manipulated such that the pointer values are A1# and A0# for word promoted byte accesses or cacheable accesses. For word promoted short accesses or cacheable accesses, the pointer values are A1# and A0. The present invention offers increased flexibility in interfacing a single-endian microprocessor with bi-endian systems. The present invention provides easy interfacing without undue or overly complex modifications to existing circuits.

摘要翻译： 一种用于在单端微处理器中执行双端字节和短接入的方法和装置。 本发明用于计算机系统中的微处理器或微处理器。 本发明提供了一种单端微处理器，其利用用于操纵访问地址的两个最低有效位的装置来指向在访问双端外部存储器期间返回的正确子字数据的单字访问到字访问 。 用于操纵地址位的方法也用于允许单端数据高速缓存与双端外部存储器一起操作。 地址的两个LSB被操纵，使得指针值是用于字提升字节访问或可缓存访问的A1＃和A0＃。 对于字提升的短访问或可缓存访问，指针值为A1＃和A0。 本发明提供了将单端微处理器与双端系统连接的增加的灵活性。 本发明提供了容易的接口，而没有对现有电路进行过度或过度复杂的修改。

公开(公告)号：US5749092A

公开(公告)日：1998-05-05

申请号：US789455

申请日：1997-01-27

申请人： Jay Heeb ,  Sunil Shenoy ,  Jimmy Wong

发明人： Jay Heeb ,  Sunil Shenoy ,  Jimmy Wong

IPC分类号： G06F12/08

CPC分类号： G06F12/0835 ,  G06F12/0837

摘要： A microprocessor and method which allows data consistency to be maintained between a memory which is external to the microprocessor and a data cache unit. The microprocessor has a central processing unit coupled to a local bus. A direct memory access unit coupled to the central processing unit for loading data from and storing data to the direct access memory unit. The local bus is coupled to a system bus and has a bus control unit controlling the loading and storing of data on the system bus. The system bus transfers data external to the microprocessor using the bus control unit upon instructions from the central processing unit. A data cache unit is coupled to the local bus and selectively stores a copy of data loaded by the bus control unit and receives a memory address from the local bus during a memory access by either the central processing unit or the direct memory access unit. The microprocessor employs a mechanism that invalidates copy data when the memory access is a store by the direct memory access unit when a cache hit is detected. Further, the microprocessor employs a mechanism that designates as non-cacheable the loading of data by the direct access memory unit, even though the data was previously designated as cachable, preventing the data cache unit from performing any action, namely the overwriting of more critical data within the data cache unit.

摘要翻译： 一种允许在微处理器外部的存储器与数据高速缓存单元之间保持数据一致性的微处理器和方法。 微处理器具有耦合到本地总线的中央处理单元。 耦合到中央处理单元的直接存储器存取单元，用于从直接访问存储单元加载数据并将数据存储到直接存取存储器单元。 本地总线耦合到系统总线，并具有控制系统总线上数据加载和存储的总线控制单元。 根据中央处理单元的指示，系统总线使用总线控制单元将数据外部传送到微处理器。 数据高速缓存单元耦合到本地总线，并且选择性地存储由总线控制单元加载的数据的副本，并且在由中央处理单元或直接存储器访问单元进行的存储器访问期间从本地总线接收存储器地址。 当检测到高速缓存命中时，微处理器采用当存储器存取是由直接存储器访问单元存储时使复制数据无效的机制。 此外，即使数据先前被指定为可高速缓存，微处理器也采用一种机制，即将数据指定为不可高速缓存的直接访问存储器单元的数据加载，从而防止数据高速缓存单元执行任何动作，即重写更关键的 数据缓存单元内的数据。

公开(公告)号：US5590368A

公开(公告)日：1996-12-31

申请号：US508318

申请日：1995-07-27

申请人： Jay Heeb ,  Sunil Shenoy ,  Jimmy Wong

发明人： Jay Heeb ,  Sunil Shenoy ,  Jimmy Wong

IPC分类号： G06F9/312 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F9/3867

摘要： A dynamically expandable pipeline in a microprocessor. The present invention is used in a microprocessor or a microprocessor in a computer system. The present invention delays execution of a cacheable LOAD instruction by a bus controller for one cycle to allow sufficient time for "hit or miss" detection by a data cache unit. The present invention dynamically expands the instruction pipeline for cacheable LOAD instructions that "miss" an on-chip data cache when the LOAD is followed by another instruction that uses the bus controller. The dynamic pipeline allows time for the "hit or miss" detection by the data cache unit without unnecessarily degrading pipeline performance. The present invention offers increased overall microprocessor and computer system performance by allowing efficient implementation of an on-chip data cache. The present invention provides increased performance without undue or overly complex modifications to existing pipeline or data cache circuits.

摘要翻译： 微处理器中的动态可扩展管线。 本发明用于计算机系统中的微处理器或微处理器。 本发明通过总线控制器延迟执行可缓存的LOAD指令一个周期，以允许由数据高速缓存单元进行“命中”或“未命中”检测的足够时间。 本发明动态地扩展了当LOAD遵循使用总线控制器的另一个指令时，可以丢弃片上数据高速缓存的可缓存LOAD指令的指令流水线。 动态流水线允许数据高速缓存单元进行“命中或未命中”检测的时间，而不会不必要地降低流水线性能。 本发明通过允许有效实现片上数据高速缓存来提供增加的总体微处理器和计算机系统性能。 本发明提供增加的性能，而不会对现有流水线或数据高速缓存电路进行过度或过度复杂的修改。

公开(公告)号：US09158355B2

公开(公告)日：2015-10-13

申请号：US12215760

申请日：2008-06-30

申请人： Sehat Sutardja ,  Hong-Yi Chen ,  Premanand Sakarda ,  Mark N. Fullerton ,  Jay Heeb

发明人： Sehat Sutardja ,  Hong-Yi Chen ,  Premanand Sakarda ,  Mark N. Fullerton ,  Jay Heeb

IPC分类号： G06F15/76 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

CPC分类号： G06F1/3293 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/38 ,  G06F9/3885 ,  G06F9/461 ,  G06F9/4856 ,  G06F9/4893 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D10/24 ,  Y02D10/32 ,  Y02D50/20

摘要： A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled.

摘要翻译： 核心交换系统包括模式切换模块，其接收切换信号以在第一模式和第二模式之间切换操作。 在第一模式期间，与应用相关联的指令由第一不对称核执行，而第二非对称核是不活动的。 在第二模式期间，指令由第二非对称核执行，第一非对称核是不活动的。 核心激活模块在禁止中断之后停止第一个非对称核心处理应用程序。 状态转移模块将第一不对称核的状态转移到第二不对称核。 核心激活模块允许第二非对称核继续执行指令，中断被使能。

公开(公告)号：US06664775B1

公开(公告)日：2003-12-16

申请号：US09643082

申请日：2000-08-21

申请人： Lawrence T. Clark ,  Michael W. Morrow ,  Gregory B. Tucker ,  Yuan-Po Ypt Tseng ,  Ali Minaei ,  Jay Heeb

发明人： Lawrence T. Clark ,  Michael W. Morrow ,  Gregory B. Tucker ,  Yuan-Po Ypt Tseng ,  Ali Minaei ,  Jay Heeb

IPC分类号： H02J312

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.

摘要翻译： 简而言之，根据本发明的一个实施例，集成电路具有电压调节器和时钟分频器，其可用于调整集成电路的工作频率和/或电压电位以降低集成电路的功耗，同时 在运行。

公开(公告)号：US06425086B1

公开(公告)日：2002-07-23

申请号：US09302560

申请日：1999-04-30

申请人： Lawrence T. Clark ,  Bart McDaniel ,  Jay Heeb ,  Tom J. Adelmeyer

发明人： Lawrence T. Clark ,  Bart McDaniel ,  Jay Heeb ,  Tom J. Adelmeyer

IPC分类号： G06F132

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

摘要翻译： 简而言之，根据本发明的一个实施例，系统包括：处理器，电压调节器和存储器。 电压调节器耦合到处理器以调整处理器的工作电压。 存储器通过存储器总线耦合到处理器。 存储器已经存储有处理器指令，当处理器执行时，该指令导致处理器的工作频率的修改并且导致处理器的工作电压的调整，至少部分地基于处理器的动态变化 处理器的处理负载。

公开(公告)号：US5889975A

公开(公告)日：1999-03-30

申请号：US746285

申请日：1996-11-07

申请人： Paul G. Meyer ,  Stephen Strazdus ,  Dennis O'Connor ,  Thomas Adelmeyer ,  Jay Heeb ,  Avery Topps

发明人： Paul G. Meyer ,  Stephen Strazdus ,  Dennis O'Connor ,  Thomas Adelmeyer ,  Jay Heeb ,  Avery Topps

IPC分类号： G06F9/38

CPC分类号： G06F9/3802 ,  G06F9/3867

摘要： A processor core suitable for use with a wide variety of instruction fetch units. The processor core contains a plurality of pipe stages including an instruction pointer generation stage and a decode stage. The core bundles all control necessary for downstream pipeline operation with an instruction address in a first stage. The bundle is transmitted outside the core to the instruction fetch unit. The instruction fetch unit fetches the instruction and adds it to the bundle, before forwarding the bundle as modified back within the core and down the pipeline. In this way, an external pipe stage is introduced providing a connection between discontinuous pipe stages in the core. Additionally, by bundling the control signals and address information in a single bundle that traverses the external pipe stage as a group, synchronization concerns are reduced or eliminated.

摘要翻译： 适用于各种指令提取单元的处理器核心。 处理器核心包括多个管级，包括指令指针生成级和解码级。 核心将下游管道运行所需的所有控制与第一阶段的指令地址进行捆绑。 捆绑包在核心外部传送到指令提取单元。 指令提取单元获取指令并将其添加到捆绑包中，然后在内核中转发捆绑包，然后在管道中进行修改。 以这种方式，引入外部管段，提供芯中不连续管段之间的连接。 此外，通过将跨越外部管道级的单个束中的控制信号和地址信息捆绑为一组，减少或消除了同步问题。

公开(公告)号：US06519707B2

公开(公告)日：2003-02-11

申请号：US09951109

申请日：2001-09-10

申请人： Lawrence T. Clark ,  Bart McDaniel ,  Jay Heeb ,  Tom J. Adelmeyer

发明人： Lawrence T. Clark ,  Bart McDaniel ,  Jay Heeb ,  Tom J. Adelmeyer

IPC分类号： G06F132

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

公开(公告)号：US20080288748A1

公开(公告)日：2008-11-20

申请号：US12215760

申请日：2008-06-30

申请人： Sehat Sutardja ,  Hong-Yi Chen ,  Premanand Sakarda ,  Mark N. Fullerton ,  Jay Heeb

发明人： Sehat Sutardja ,  Hong-Yi Chen ,  Premanand Sakarda ,  Mark N. Fullerton ,  Jay Heeb

IPC分类号： G06F15/80 ,  G06F9/00

CPC分类号： G06F1/3293 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/38 ,  G06F9/3885 ,  G06F9/461 ,  G06F9/4856 ,  G06F9/4893 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D10/24 ,  Y02D10/32 ,  Y02D50/20

摘要： A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled.

摘要翻译： 核心交换系统包括模式切换模块，其接收切换信号以在第一模式和第二模式之间切换操作。 在第一模式期间，与应用相关联的指令由第一不对称核执行，而第二非对称核是不活动的。 在第二模式期间，指令由第二非对称核执行，第一非对称核是不活动的。 核心激活模块在禁止中断之后停止第一个非对称核心处理应用程序。 状态转移模块将第一不对称核的状态转移到第二不对称核。 核心激活模块允许第二非对称核继续执行指令，中断被使能。

公开(公告)号：US20080263324A1

公开(公告)日：2008-10-23

申请号：US12145660

申请日：2008-06-25

申请人： Sehat Sutardja ,  Hong-Yi Chen ,  Premanand Sakarda ,  Mark N. Fullerton ,  Jay Heeb

发明人： Sehat Sutardja ,  Hong-Yi Chen ,  Premanand Sakarda ,  Mark N. Fullerton ,  Jay Heeb

IPC分类号： G06F9/00

CPC分类号： G06F1/3293 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/38 ,  G06F9/3885 ,  G06F9/461 ,  G06F9/4856 ,  G06F9/4893 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D10/24 ,  Y02D10/32 ,  Y02D50/20

摘要： A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when the system operates in the second mode. The core switching module switches operation of the system between the first mode and the second mode. The core switching module selectively stops processing of the application by the first asymmetric core after receiving a first control signal. The core switching module transfers a first state of the first asymmetric core to the second asymmetric core. The second asymmetric core resumes executing the application in the second mode.

摘要翻译： 系统包括第一不对称核心，第二非对称核心和核心交换模块。 当系统以第一模式操作时，第一非对称核执行应用，并且当系统以第二模式操作时，该状态不活动。 当系统在第二模式下运行时，第二个非对称核执行应用程序。 核心交换模块在第一模式和第二模式之间切换系统的操作。 核心交换模块在接收到第一控制信号之后选择性地停止第一非对称核心处理应用程序。 核心交换模块将第一不对称核心的第一状态传送到第二不对称核心。 第二个非对称核心在第二个模式中恢复执行应用程序。