GUEST TIMER FACILITY IN A VIRTUALIZED PROCESSING SYSTEM
    1.
    发明申请
    GUEST TIMER FACILITY IN A VIRTUALIZED PROCESSING SYSTEM 有权
    虚拟化处理系统中的用户定时器设备

    公开(公告)号:US20120117564A1

    公开(公告)日:2012-05-10

    申请号:US12940391

    申请日:2010-11-05

    IPC分类号: G06F9/455

    CPC分类号: G06F9/45541

    摘要: A method includes, in a virtualized processing system, generating a local value of a first counter. The local value is accessible while executing in a first mode of the virtualized processing system. The local value is generated based on a value of a second counter and a ratio of a rate of the first counter to a rate of the second counter. The first counter is inaccessible while executing in the first mode of the virtualized processing system and accessible while executing in a second mode of the virtualized processing system. The first mode may be a guest mode and the second mode may be a host mode. The first counter may be an ACPI Power Management Timer. The second counter may be a Time Stamp Counter.

    摘要翻译: 一种方法包括在虚拟化处理系统中产生第一计数器的本地值。 在虚拟化处理系统的第一模式下执行时,可以访问本地值。 基于第二计数器的值和第一计数器的速率与第二计数器的速率的比率来生成本地值。 当在虚拟化处理系统的第一模式下执行时,第一计数器是不可访问的,并且在虚拟化处理系统的第二模式下执行时可访问。 第一模式可以是访客模式,第二模式可以是主机模式。 第一个计数器可以是ACPI电源管理定时器。 第二计数器可以是时间戳计数器。

    Address mapping in virtualized processing system
    2.
    发明授权
    Address mapping in virtualized processing system 有权
    虚拟化处理系统中的地址映射

    公开(公告)号:US08386749B2

    公开(公告)日:2013-02-26

    申请号:US12724912

    申请日:2010-03-16

    IPC分类号: G06F12/10

    CPC分类号: G06F12/1036 G06F2212/152

    摘要: A processing system has one or more processors that implement a plurality of virtual machines that are managed by a hypervisor. Each virtual machine provides a secure and isolated hardware-emulation environment for execution of one or more corresponding guest operating systems (OSs). Each guest OS, as well as the hypervisor itself, has an associated address space, identified with a corresponding “WorldID.” Further, each virtual machine and the hypervisor can manage multiple lower-level address spaces, identified with a corresponding “address space identifier” or “ASID”. The address translation logic of the processing system translates the WorldID and ASID of the current address space context of the processing system to corresponding WorldID and ASID search keys, which have fewer bits than the original identifiers and thus require less complex translation lookaside buffer (TLB) hit logic. The resulting WorldID and ASID search keys are used to perform one or more TLB lookups to obtain address mapping information related to the particular address space represented by the WorldID/ASID combination.

    摘要翻译: 处理系统具有实现由管理程序管理的多个虚拟机的一个或多个处理器。 每个虚拟机为执行一个或多个相应的客户机操作系统(OS)提供安全和隔离的硬件仿真环境。 每个客户操作系统以及虚拟机管理程序本身都具有相关联的地址空间,用相应的WorldID标识。 此外,每个虚拟机和虚拟机管理程序可以管理用相应的地址空间标识符或ASID标识的多个下级地址空间。 处理系统的地址转换逻辑将处理系统的当前地址空间上下文的WorldID和ASID将相应的WorldID和ASID搜索键转换成比原始标识符少的位,因此需要较不复杂的翻译后置缓冲器(TLB) 命中逻辑。 所产生的WorldID和ASID搜索关键字用于执行一个或多个TLB查找以获得与由WorldID / ASID组合表示的特定地址空间相关的地址映射信息。

    Guest timer facility to improve management in a virtualized processing system
    3.
    发明授权
    Guest timer facility to improve management in a virtualized processing system 有权
    访客计时器设施,以改善虚拟化处理系统的管理

    公开(公告)号:US08490089B2

    公开(公告)日:2013-07-16

    申请号:US12940391

    申请日:2010-11-05

    IPC分类号: G06F9/455 G06F1/12 G06F13/42

    CPC分类号: G06F9/45541

    摘要: A method includes, in a virtualized processing system, generating a local value of a first counter. The local value is accessible while executing in a first mode of the virtualized processing system. The local value is generated based on a value of a second counter and a ratio of a rate of the first counter to a rate of the second counter. The first counter is inaccessible while executing in the first mode of the virtualized processing system and accessible while executing in a second mode of the virtualized processing system. The first mode may be a guest mode and the second mode may be a host mode. The first counter may be an ACPI Power Management Timer. The second counter may be a Time Stamp Counter.

    摘要翻译: 一种方法包括在虚拟化处理系统中产生第一计数器的本地值。 在虚拟化处理系统的第一模式下执行时,可以访问本地值。 基于第二计数器的值和第一计数器的速率与第二计数器的速率的比率来生成本地值。 当在虚拟化处理系统的第一模式下执行时,第一计数器是不可访问的,并且在虚拟化处理系统的第二模式下执行时可访问。 第一模式可以是访客模式,第二模式可以是主机模式。 第一个计数器可以是ACPI电源管理定时器。 第二计数器可以是时间戳计数器。

    Extended page size using aggregated small pages
    4.
    发明授权
    Extended page size using aggregated small pages 有权
    使用聚合小页面扩展页面大小

    公开(公告)号:US08195917B2

    公开(公告)日:2012-06-05

    申请号:US12496335

    申请日:2009-07-01

    IPC分类号: G06F12/10

    摘要: A processor including a virtual memory paging mechanism. The virtual memory paging mechanism enables an operating system operating on the processor to use pages of a first size and a second size, the second size being greater than the first size. The mechanism further enables the operating system to use superpages including two or more contiguous pages of the first size. The size of a superpage is less than the second size. The processor further includes a page table having a separate entry for each of the pages included in each superpage. The operating system accesses each superpage using a single virtual address. The mechanism interprets a single entry in a translation lookaside buffer TLB as referring to a region of memory comprising a set of pages that correspond to a superpage in response to detecting a superpage enable indicator associated with the entry in the TLB is asserted.

    摘要翻译: 一种包括虚拟存储器寻呼机构的处理器。 虚拟存储器分页机构使得在处理器上操作的操作系统能够使用具有第一尺寸和第二尺寸的页面,第二尺寸大于第一尺寸。 该机制进一步使得操作系统能够使用包括第一尺寸的两个或更多个连续页面的超级页面。 超级页面的大小小于第二个大小。 处理器还包括页表,其具有用于每个超级页面中包括的每个页面的单独条目。 操作系统使用单个虚拟地址访问每个超级页面。 该机制将翻译后备缓存器TLB中的单个条目解释为响应于检测到与TLB中的条目相关联的超级页面使能指示符被断言的引用包括与超级页面相对应的页面的存储器区域。

    ADDRESS MAPPING IN VIRTUALIZED PROCESSING SYSTEM
    5.
    发明申请
    ADDRESS MAPPING IN VIRTUALIZED PROCESSING SYSTEM 有权
    虚拟化处理系统中的地址映射

    公开(公告)号:US20110231630A1

    公开(公告)日:2011-09-22

    申请号:US12724912

    申请日:2010-03-16

    IPC分类号: G06F12/10

    CPC分类号: G06F12/1036 G06F2212/152

    摘要: A processing system has one or more processors that implement a plurality of virtual machines that are managed by a hypervisor. Each virtual machine provides a secure and isolated hardware-emulation environment for execution of one or more corresponding guest operating systems (OSs). Each guest OS, as well as the hypervisor itself, has an associated address space, identified with a corresponding “WorldID.” Further, each virtual machine and the hypervisor can manage multiple lower-level address spaces, identified with a corresponding “address space identifier” or “ASID”. The address translation logic of the processing system translates the WorldID and ASID of the current address space context of the processing system to corresponding WorldID and ASID search keys, which have fewer bits than the original identifiers and thus require less complex translation lookaside buffer (TLB) hit logic. The resulting WorldID and ASID search keys are used to perform one or more TLB lookups to obtain address mapping information related to the particular address space represented by the WorldID/ASID combination.

    摘要翻译: 处理系统具有实现由管理程序管理的多个虚拟机的一个或多个处理器。 每个虚拟机为一个或多个相应的客户操作系统(OS)的执行提供了安全和隔离的硬件仿真环境。 每个客户操作系统以及虚拟机管理程序本身都具有相关联的地址空间,用相应的“WorldID”标识。此外,每个虚拟机和管理程序可以管理多个下级地址空间,用相应的“地址空间标识符 “或”ASID“。 处理系统的地址转换逻辑将处理系统的当前地址空间上下文的WorldID和ASID将相应的WorldID和ASID搜索键转换成比原始标识符少的位,因此需要较不复杂的翻译后置缓冲器(TLB) 命中逻辑。 所产生的WorldID和ASID搜索关键字用于执行一个或多个TLB查找以获得与由WorldID / ASID组合表示的特定地址空间相关的地址映射信息。

    EXTENDED PAGE SIZE USING AGGREGATED SMALL PAGES
    6.
    发明申请
    EXTENDED PAGE SIZE USING AGGREGATED SMALL PAGES 有权
    扩展页尺寸使用聚集小页

    公开(公告)号:US20110004739A1

    公开(公告)日:2011-01-06

    申请号:US12496335

    申请日:2009-07-01

    IPC分类号: G06F12/10 G06F12/00

    摘要: A processor including a virtual memory paging mechanism. The virtual memory paging mechanism enables an operating system operating on the processor to use pages of a first size and a second size, the second size being greater than the first size. The mechanism further enables the operating system to use superpages including two or more contiguous pages of the first size. The size of a superpage is less than the second size. The processor further includes a page table having a separate entry for each of the pages included in each superpage. The operating system accesses each superpage using a single virtual address. The mechanism interprets a single entry in a translation lookaside buffer TLB as referring to a region of memory comprising a set of pages that correspond to a superpage in response to detecting a superpage enable indicator associated with the entry in the TLB is asserted.

    摘要翻译: 一种包括虚拟存储器寻呼机构的处理器。 虚拟存储器分页机构使得在处理器上操作的操作系统能够使用具有第一尺寸和第二尺寸的页面,第二尺寸大于第一尺寸。 该机制进一步使得操作系统能够使用包括第一尺寸的两个或更多个连续页面的超级页面。 超级页面的大小小于第二个大小。 处理器还包括页表,其具有用于每个超级页面中包括的每个页面的单独条目。 操作系统使用单个虚拟地址访问每个超级页面。 该机制将翻译后备缓存器TLB中的单个条目解释为响应于检测到与TLB中的条目相关联的超级页面使能指示符被断言的引用包括与超级页面相对应的页面的存储器区域。