公开(公告)号：US08228746B2

公开(公告)日：2012-07-24

申请号：US12650380

申请日：2009-12-30

申请人： Dae Suk Kim ,  Seoung Hyun Kang

发明人： Dae Suk Kim ,  Seoung Hyun Kang

IPC分类号： G11C7/00

CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C29/1201 ,  G11C29/48

摘要： A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: an address pad; an address pad buffer section configured to selectively receive a signal of the address pad; a data input buffer section configured to selectively receive the signal of the address pad; and a signal control section configured to selectively provide a path of the signal of the address pad to the address buffer section and the data input buffer section.

摘要翻译： 提供半导体存储装置。 半导体存储装置包括：地址板; 配置为选择性地接收地址块的信号的地址块缓冲器部分; 数据输入缓冲器部分，被配置为选择性地接收地址焊盘的信号; 以及信号控制部分，被配置为选择性地将地址块的信号的路径提供给地址缓冲器部分和数据输入缓冲器部分。

公开(公告)号：US08053346B2

公开(公告)日：2011-11-08

申请号：US12109637

申请日：2008-04-25

申请人： Nam Gyu Ryu ,  Ho Ryong Kim ,  Won John Choi ,  Jae Hwan Kim ,  Seoung Hyun Kang ,  Young Hee Yoon

发明人： Nam Gyu Ryu ,  Ho Ryong Kim ,  Won John Choi ,  Jae Hwan Kim ,  Seoung Hyun Kang ,  Young Hee Yoon

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L27/088

CPC分类号： H01L27/0207 ,  Y10S438/926

摘要： A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.

摘要翻译： 半导体器件中的栅极形成为具有保护栅极的伪栅极图案。 形成金属线以为半导体器件供电并传输信号。 半导体器件包括四耦合接收器型输入/输出缓冲器。 半导体器件形成有在有源区域上延伸的栅极线和位于有源区域外部的栅极焊盘。 栅极线和栅极焊盘相邻，使得栅极线和栅极焊盘的一侧形成一条线。 也可以应用虚拟门。 半导体器件包括向具有多个单元的块提供功率的第一金属线图案，向单元传输信号的第二金属线图案和沿纵向方向分割的虚拟金属线图案。

公开(公告)号：US20120007187A1

公开(公告)日：2012-01-12

申请号：US13242188

申请日：2011-09-23

申请人： Nam Gyu RYU ,  Ho Ryong KIM ,  Won John CHOI ,  Jae Hwan KIM ,  Seoung Hyun KANG ,  Young Hee YOON

发明人： Nam Gyu RYU ,  Ho Ryong KIM ,  Won John CHOI ,  Jae Hwan KIM ,  Seoung Hyun KANG ,  Young Hee YOON

IPC分类号： H01L27/092

CPC分类号： H01L27/0207 ,  Y10S438/926

摘要： A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.

摘要翻译： 半导体器件中的栅极形成为具有保护栅极的伪栅极图案。 形成金属线以为半导体器件供电并传输信号。 半导体器件包括四耦合接收器型输入/输出缓冲器。 半导体器件形成有在有源区域上延伸的栅极线和位于有源区域外部的栅极焊盘。 栅极线和栅极焊盘相邻，使得栅极线和栅极焊盘的一侧形成一条线。 也可以应用虚拟门。 半导体器件包括向具有多个单元的块提供功率的第一金属线图案，向单元传输信号的第二金属线图案和沿纵向方向分割的虚拟金属线图案。

公开(公告)号：US20080265335A1

公开(公告)日：2008-10-30

申请号：US12109637

申请日：2008-04-25

申请人： Nam Gyu RYU ,  Ho Ryong KIM ,  Won John CHOI ,  Jae Hwan KIM ,  Seoung Hyun KANG ,  Young Hee YOON

发明人： Nam Gyu RYU ,  Ho Ryong KIM ,  Won John CHOI ,  Jae Hwan KIM ,  Seoung Hyun KANG ,  Young Hee YOON

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L27/0207 ,  Y10S438/926

摘要： A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.

摘要翻译： 半导体器件中的栅极形成为具有保护栅极的伪栅极图案。 形成金属线以为半导体器件供电并传输信号。 半导体器件包括四耦合接收器型输入/输出缓冲器。 半导体器件形成有在有源区域上延伸的栅极线和位于有源区域外部的栅极焊盘。 栅极线和栅极焊盘相邻，使得栅极线和栅极焊盘的一侧形成一条线。 也可以应用虚拟门。 半导体器件包括向具有多个单元的块提供功率的第一金属线图案，向单元传输信号的第二金属线图案和沿纵向方向分割的虚拟金属线图案。

公开(公告)号：US20110128800A1

公开(公告)日：2011-06-02

申请号：US12650380

申请日：2009-12-30

申请人： Dae Suk Kim ,  Seoung Hyun Kang

发明人： Dae Suk Kim ,  Seoung Hyun Kang

IPC分类号： G11C7/00 ,  G11C8/06 ,  G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C29/1201 ,  G11C29/48

摘要： A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: an address pad; an address pad buffer section configured to selectively receive a signal of the address pad; a data input buffer section configured to selectively receive the signal of the address pad; and a signal control section configured to selectively provide a path of the signal of the address pad to the address buffer section and the data input buffer section.

摘要翻译： 提供半导体存储装置。 半导体存储装置包括：地址板; 配置为选择性地接收地址块的信号的地址块缓冲器部分; 数据输入缓冲器部分，被配置为选择性地接收地址焊盘的信号; 以及信号控制部分，被配置为选择性地将地址块的信号的路径提供给地址缓冲器部分和数据输入缓冲器部分。