公开(公告)号：US5260907A

公开(公告)日：1993-11-09

申请号：US701527

申请日：1991-05-16

申请人： Seung M. Kim

发明人： Seung M. Kim

IPC分类号： G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C29/83

摘要： A repair circuit for integrated circuits adapted for selecting and repairing a storage cell having a fault, and a main fuse adapted for operating the repair circuit. The repair circuit comprises a plurality of p-channel MOSFETs and a plurality of fuses. A NAND gate has as inputs, an output signal from said repair circuit and a control signal. The control signal is generated as the address of the selected cell is varied. The control signal is a pulse which transits from a low lever to a high level and back to a low level again as the address is varied. The repair circuit reduces power consumption in integrated circuits by allowing current to flow therein only when the address of the selected cell is varied.

摘要翻译： 一种用于选择和修复具有故障的存储单元的集成电路的修复电路和适用于操作该修复电路的主熔丝。 修复电路包括多个p沟道MOSFET和多个保险丝。 NAND门具有作为输入的来自所述修复电路的输出信号和控制信号。 当所选择的单元的地址变化时，产生控制信号。 控制信号是一个脉冲，从低电平转换到高电平并再次回到低电平，因为地址变化。 修复电路通过仅当所选择的单元的地址变化时允许电流流入集成电路中才能降低功耗。

公开(公告)号：US5057711A

公开(公告)日：1991-10-15

申请号：US530819

申请日：1990-05-30

申请人： Jong S. Lee ,  Seung M. Kim ,  Joo W. Park

发明人： Jong S. Lee ,  Seung M. Kim ,  Joo W. Park

IPC分类号： H03K17/687 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/01742 ,  H03K19/00361

摘要： An output buffer circuit for an integrated circuit for outputting an amplified signal from a sense amplifier which senses information stored in a memory cell of random access memory for improving operation of the integrated circuit is disclosed. The output buffer circuit comprises NAND gates ND1, ND2 operatively connected to the output of the sense amplifier to receive first and second output signals S1, S2, and operatively connected to receive a control signal .phi.1 from the integrated circuit which operates the memory cell to read. A MOSFET Q1 and a MOSFET Q2 are utilized with both MOSFETs turning on or off depending upon the signals applied to their gates. An output loading capacitor CL is operatively connected to the junction P4 and to the ground. A logic combination means 10 connected to junctions P1, P2 performs a logical combination of the signal applied through the junction P4 and the control signal .phi.1 applied to the input points of the logic combination means. An output means 20 is connected between the logic combination means 10 and the junction P4, thereby controlling the output level of the output buffer circuit to a middle level depending upon the signal from the logic combination means.

摘要翻译： 公开了一种用于从感测放大器输出放大信号的集成电路的输出缓冲电路，其感测存储在随机存取存储器的存储单元中的信息，以改善集成电路的操作。 输出缓冲器电路包括可操作地连接到读出放大器的输出的NAND门ND1，ND2，以接收第一和第二输出信号S1，S2，并且可操作地连接以从操作存储器单元的集成电路接收控制信号phi 1 读。 根据施加到其栅极的信号，使用MOSFET Q1和MOSFET Q2，两个MOSFET导通或关断。 输出负载电容器CL可操作地连接到接点P4和接地。 连接到结点P1，P2的逻辑组合装置10执行通过结点P4施加的信号和施加到逻辑组合装置的输入点的控制信号phi 1的逻辑组合。 输出装置20连接在逻辑组合装置10和接点P4之间，从而根据来自逻辑组合装置的信号将输出缓冲器电路的输出电平控制到中间电平。