公开(公告)号：US20150137252A1

公开(公告)日：2015-05-21

申请号：US14474484

申请日：2014-09-02

Applicant: Sang-Hoon Baek ,  Sang-Kyu Oh ,  Na-Ya Ha ,  Seung-Weon Paek ,  Tae-Joong Song

Inventor： Sang-Hoon Baek ,  Sang-Kyu Oh ,  Na-Ya Ha ,  Seung-Weon Paek ,  Tae-Joong Song

IPC: G06F17/50 ,  H01L27/11 ,  H01L27/115 ,  H01L27/108

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/6681

Abstract: A layout design system includes a processor; a storage unit configured to store a first unit design having a first area, wherein in the first unit design, a termination is not placed on a border thereof; and a design module configured to generate a second unit design having a second area larger than the first area by placing the termination on a border of the first unit.

Abstract translation: 布局设计系统包括处理器; 存储单元，其被配置为存储具有第一区域的第一单元设计，其中在所述第一单元设计中，终端不被放置在其边界上; 以及设计模块，其被配置为通过将所述终端放置在所述第一单元的边界上来生成具有大于所述第一区域的第二区域的第二单元设计。

公开(公告)号：US20160283634A1

公开(公告)日：2016-09-29

申请号：US14991330

申请日：2016-01-08

Applicant: Byung-Moo KIM ,  Seung Weon PAEK

Inventor： Byung-Moo KIM ,  Seung Weon PAEK

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L21/76807 ,  H01L21/76816 ,  H01L27/0207 ,  H01L27/11582 ,  H01L28/00

Abstract: A method of designing a layout of a semiconductor device includes preparing a layout for a semiconductor integrated circuit, the preparing of the layout including providing lower and upper metal patterns and via patterns, which are vertically interposed between the lower and upper metal patterns, performing a retargeting process on the lower and upper metal patterns, classifying the via patterns to extract at least one risk via from the via patterns and changing a position of the risk via. During the changing of the position of the risk via, all of the via patterns, other than the risk via, are unchanged in position thereof. Related systems and computer program products are disclosed.

Abstract translation: 设计半导体器件的布局的方法包括制备用于半导体集成电路的布局，准备布局包括提供垂直插入在下金属图案和上金属图案之间的下金属图案和上金属图案和通孔图案， 对下部和上部金属图案进行重新定向处理，对通孔图案进行分类以从通孔图案中提取至少一个风险，并改变风险位置。 在改变风险位置的过程中，除了风险通过之外的所有通道图案在其位置上都不变。 公开了相关系统和计算机程序产品。

公开(公告)号：US07001710B2

公开(公告)日：2006-02-21

申请号：US10623419

申请日：2003-07-18

Applicant: Sang-Tae Choi ,  Seung-Weon Paek

Inventor： Sang-Tae Choi ,  Seung-Weon Paek

IPC: G03C5/00

CPC classification number: G03F7/40 ,  H01L21/0276 ,  H01L21/0338 ,  H01L21/31144 ,  Y10S430/143 ,  Y10S430/146

Abstract: A method for forming an ultra fine contact hole includes: forming a KrF photoresist pattern on a semiconductor substrate providing an insulation layer, the KrF photoresist pattern exposing a predetermined region for forming a contact hole on the insulation layer; forming a chemically swelling process (CSP) chemical material-containing layer being reactive to the KrF photoresist pattern on an entire surface of the semiconductor substrate; forming a chemical material-containing pattern encompassing the KrF photoresist pattern by reacting the chemical material-containing layer with the KrF photoresist pattern through a chemically swelling process to decrease a critical dimension of the contact hole; rinsing the semiconductor substrate; and increasing a thickness of a sidewall of the chemical material-containing pattern to a predetermined thickness by performing a resist flow process (RFP) that makes the chemical material-containing pattern flowed to decrease the critical dimension (CD) of the contact hole.

Abstract translation: 一种用于形成超细接触孔的方法包括：在提供绝缘层的半导体衬底上形成KrF光致抗蚀剂图案，所述KrF光致抗蚀剂图案暴露用于在绝缘层上形成接触孔的预定区域; 形成在所述半导体衬底的整个表面上与所述KrF光致抗蚀剂图案反应的化学溶胀过程（CSP）含化学材料层; 通过化学溶胀过程使包含化学材料的层与KrF光致抗蚀剂图案反应来形成包含KrF光致抗蚀剂图案的含化学材料的图案，以减小接触孔的临界尺寸; 冲洗半导体衬底; 并且通过执行使含化学材料的图案流动以降低接触孔的临界尺寸（CD）的抗蚀剂流动过程（RFP）将含化学材料的图案的侧壁的厚度增加到预定厚度。

公开(公告)号：US09904753B2

公开(公告)日：2018-02-27

申请号：US14991330

申请日：2016-01-08

Applicant: Byung-Moo Kim ,  Seung Weon Paek

Inventor： Byung-Moo Kim ,  Seung Weon Paek

IPC: G06F17/50 ,  H01L27/11582 ,  H01L27/02 ,  H01L21/768

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L21/76807 ,  H01L21/76816 ,  H01L27/0207 ,  H01L27/11582 ,  H01L28/00

Abstract: A method of designing a layout of a semiconductor device includes preparing a layout for a semiconductor integrated circuit, the preparing of the layout including providing lower and upper metal patterns and via patterns, which are vertically interposed between the lower and upper metal patterns, performing a retargeting process on the lower and upper metal patterns, classifying the via patterns to extract at least one risk via from the via patterns and changing a position of the risk via. During the changing of the position of the risk via, all of the via patterns, other than the risk via, are unchanged in position thereof. Related systems and computer program products are disclosed.