公开(公告)号：US5946707A

公开(公告)日：1999-08-31

申请号：US808526

申请日：1997-02-28

申请人： Shahe H. Krakirian

发明人： Shahe H. Krakirian

IPC分类号： G06F11/10 ,  H03M13/00 ,  G06F12/00

CPC分类号： G06F11/1076 ,  H03M13/00

摘要： A method and apparatus for performing XOR operations on a hard disk drive are provided, which optimize the buffer bandwidth with minimal logic added to the hard disk controller integrated circuit. This is achieved by first storing data from a first source in the buffer memory in an interleaved fashion (i.e. at memory locations having addresses k, k+2 . . . ,k+2n-2) and then sequentially reading each bit set from the buffer memory, XORing it with a corresponding bit set read from a second source and writing the result at the next consecutive location in the buffer memory (i.e. at memory locations having addresses k+1, k+3 . . . k+2n-1). The method can be implemented on existing hard disk controllers with minimal modifications to the hardware. In addition, an embodiment of the invention allows for decoupling of the XOR operation from disk and host transfers, allowing each of those transfers to occur at their maximum rate and using the remaining buffer bandwidth for the XOR operation.

摘要翻译： 提供了一种用于在硬盘驱动器上执行XOR操作的方法和装置，其以最小的逻辑增加到硬盘控制器集成电路来优化缓冲器带宽。 这通过首先以交错方式（即，在具有地址k，k + 2，...，k + 2n-2的存储器位置）处从缓冲存储器中的第一源存储数据，然后从 缓冲存储器，将其与从第二源读取的相应位组进行异或，并将结果写入缓冲存储器中的下一个连续位置（即，在具有地址k + 1，k + 3 ... k + 2n-1的存储单元处 ）。 该方法可以在现有硬盘控制器上实现，同时对硬件进行最小的修改。 此外，本发明的一个实施例允许将异或操作与磁盘和主机传输分离，从而允许每个传输以其最大速率发生，并且使用用于异或操作的剩余缓冲器带宽。

公开(公告)号：US5634081A

公开(公告)日：1997-05-27

申请号：US205002

申请日：1994-03-01

申请人： Shahe H. Krakirian

发明人： Shahe H. Krakirian

IPC分类号： G06F3/06 ,  G06F13/12 ,  G06F13/38 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F3/061 ,  G06F13/126 ,  G06F13/385 ,  G06F3/0659 ,  G06F3/0676

摘要： A hard disk controller integrated circuit of a SCSI target device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution of an autoread or an autowrite SCSI command without waiting for a communication from a microprocessor of the SCSI target device. In some embodiments, the command is determined to be either an autotransfer command or a non-autotransfer command. If the command is a non-autotransfer command, then the sequencer does not proceed directly to the data transfer phase but rather requires microprocessor intervention before proceeding to the data transfer phase. In some embodiments, an autotransfer command (such as an autoread or an autowrite command) is carried out by the disk drive controller integrated circuit with only two interrupts being generated to the microprocessor: one after receiving the autotransfer command from the initiator; and one after data transfer of the autotransfer command is complete. The hard disk controller integrated circuit automatically sends the status byte and command complete message if there is no queue tag collision as indicated by a cleared tag not okay flag.

摘要翻译： SCSI目标设备的硬盘控制器集成电路包括定序器，其使SCSI总线在执行自动读取或自动写入SCSI命令期间从命令总线相位转换到数据传输总线相位而不等待来自微处理器的通信 的SCSI目标设备。 在一些实施例中，该命令被确定为自动转移命令或非自动转移命令。 如果命令是非自动转换命令，则定序器不会直接进行到数据传输阶段，而是在进行数据传输阶段之前需要微处理器干预。 在一些实施例中，自动转移命令（例如自动读取或自动写入命令）由盘驱动器控制器集成电路执行，其中仅向微处理器生成两个中断：一个在从发起者接收到自动转发命令之后; 并且自动传输命令的数据传输之后完成。 如果没有排队标签冲突，硬盘控制器集成电路会自动发送状态字节和命令完成消息，如清除标签不正常标志所示。

公开(公告)号：US6064247A

公开(公告)日：2000-05-16

申请号：US72916

申请日：1998-05-04

申请人： Shahe H. Krakirian

发明人： Shahe H. Krakirian

IPC分类号： G06F1/06 ,  G06F1/08 ,  G06F1/04

CPC分类号： G06F1/08 ,  G06F1/06

摘要： A method and apparatus for generating multiple frequency clock signals using a single input clock signal are provided. Each clock signal generated has a cycle time that is an integer multiple of the input clock cycle time. The fastest clock signal, i.e., the clock signal with the highest frequency generated has the same cycle time as the input clock. The rising edges of all the clock signals generated are synchronized and each clock signal generated has an approximate duty cycle of 50%. This is achieved by first applying the input clock signal to an input terminal of a plurality of registers and of a frequency control module of the signal generator, presenting control signals to input terminals of the registers and of the frequency control module, and generating a plurality of output clock signals in the frequency control module, dependent on the input clock signal and on the control signals.

摘要翻译： 提供了使用单个输入时钟信号产生多个频率时钟信号的方法和装置。 所生成的每个时钟信号的周期时间是输入时钟周期时间的整数倍。 最快的时钟信号，即产生的频率最高的时钟信号与输入时钟具有相同的周期时间。 产生的所有时钟信号的上升沿被同步，并且所生成的每个时钟信号具有50％的近似占空比。 这通过首先将输入时钟信号施加到多个寄存器的输入端和信号发生器的频率控制模块来实现，向控制寄存器和频率控制模块的输入端提供控制信号，并产生多个 的频率控制模块中的输出时钟信号，取决于输入时钟信号和控制信号。

公开(公告)号：US07120728B2

公开(公告)日：2006-10-10

申请号：US10209694

申请日：2002-07-31

申请人： Shahe H. Krakirian ,  Richard A. Walter ,  Subbaro Arumilli ,  Cirillo Lino Costantino ,  L. Vincent M. Isip ,  Subhojit Roy ,  Naveen S. Maveli ,  Daniel Ji Yong Park Chung ,  Stephen D. Elstad ,  Dennis H. Makishima ,  Daniel Y. Chung

发明人： Shahe H. Krakirian ,  Richard A. Walter ,  Subbaro Arumilli ,  Cirillo Lino Costantino ,  L. Vincent M. Isip ,  Subhojit Roy ,  Naveen S. Maveli ,  Daniel Ji Yong Park Chung ,  Stephen D. Elstad ,  Dennis H. Makishima ,  Daniel Y. Chung

IPC分类号： G06F12/00

CPC分类号： G06F3/0626 ,  G06F3/0635 ,  G06F3/0664 ,  G06F3/067 ,  H04L41/046

摘要： Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a series of HBAs are provided in the switch unit. The HBAs connect to bridge chips and memory controllers to place the frame information in dedicated memory. Routine translation of known destinations is done by the HBA, based on a virtualization table provided by a virtualization CPU. If a frame is not in the table, it is provided to the dedicated RAM. Analysis and manipulation of the frame headers is then done by the CPU, with a new entry being made in the HBA table and the modified frames then redirected by the HBA into the fabric. This can be done in either a standalone switch environment or in combination with other switching components located in a director level switch. In an alternative embodiment, specialized hardware scans incoming frames and detects the virtualized frames which need to be redirected. The redirection is then handled by translation of the frame header information by hardware table-based logic and the translated frames are then returned to the fabric. Handling of frames not in the table and setup of hardware tables is done by an onboard CPU.

摘要翻译： 将虚拟化代理放在构成SAN结构的交换机中。 外部管理服务器提供了更高层次的虚拟化管理功能。 传统的HBA可以在主机和存储单元中使用。 在第一实施例中，在开关单元中提供一系列HBA。 HBA连接到桥芯片和存储器控制器，以将帧信息放置在专用存储器中。 基于由虚拟化CPU提供的虚拟化表，HBA完成已知目的地的常规转换。 如果一个帧不在表中，它被提供给专用的RAM。 然后由CPU完成对帧头的分析和处理，在HBA表中创建一个新条目，然后修改的帧由HBA重定向到该结构中。 这可以在独立的开关环境中或与位于导向器电平开关中的其他开关元件组合完成。 在替代实施例中，专用硬件扫描传入帧并检测需要被重定向的虚拟化帧。 然后通过基于硬件表的逻辑的帧头信息的翻译来处理重定向，然后将翻译的帧返回到结构。 处理不在表中的帧和硬件表的设置由板载CPU完成。

公开(公告)号：US5781803A

公开(公告)日：1998-07-14

申请号：US465075

申请日：1995-06-05

申请人： Shahe H. Krakirian

发明人： Shahe H. Krakirian

IPC分类号： G06F3/06 ,  G06F13/12 ,  G06F13/38 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F3/061 ,  G06F13/126 ,  G06F13/385 ,  G06F3/0659 ,  G06F3/0676

摘要： A hard disk controller integrated circuit of a SCSI target device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution of an autoread or an autowrite SCSI command without waiting for a communication from a microprocessor of the SCSI target device. In some embodiments, the command is determined to be either an autotransfer command or a non-autotransfer command. If the command is a non-autotransfer command, then the sequencer does not proceed directly to the data transfer phase but rather requires microprocessor intervention before proceeding to the data transfer phase. In some embodiments, an autotransfer command (such as an autoread or an autowrite command) is carried out by the disk drive controller integrated circuit with only two interrupts being generated to the microprocessor: one after receiving the autotransfer command from the initiator; and one after data transfer of the autotransfer command is complete. The hard disk controller integrated circuit automatically sends the status byte and command complete message if there is no potential queue tag collision as indicated by a cleared tag not okay flag.

摘要翻译： SCSI目标设备的硬盘控制器集成电路包括定序器，其使SCSI总线在执行自动读取或自动写入SCSI命令期间从命令总线相位转换到数据传输总线相位而不等待来自微处理器的通信 的SCSI目标设备。 在一些实施例中，该命令被确定为自动转移命令或非自动转移命令。 如果命令是非自动转换命令，则定序器不会直接进行到数据传输阶段，而是在进行数据传输阶段之前需要微处理器干预。 在一些实施例中，自动转移命令（例如自动读取或自动写入命令）由盘驱动器控制器集成电路执行，其中仅向微处理器生成两个中断：一个在从发起者接收到自动转发命令之后; 并且自动传输命令的数据传输之后完成。 如果没有潜在的队列标签冲突，硬盘控制器集成电路会自动发送状态字节和命令完成消息，如清除标签不正常标志所示。

公开(公告)号：US5752083A

公开(公告)日：1998-05-12

申请号：US463617

申请日：1995-06-05

申请人： Shahe H. Krakirian

发明人： Shahe H. Krakirian

IPC分类号： G06F3/06 ,  G06F13/12 ,  G06F13/38 ,  G06F13/00

CPC分类号： G06F3/061 ,  G06F13/126 ,  G06F13/385 ,  G06F3/0659 ,  G06F3/0676

摘要： A hard disk controller integrated circuit of a SCSI target-device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution of an autoread or an autowrite SCSI command without waiting for a communication from a microprocessor of the SCSI target device. In some embodiments, the command is determined to be either an autotransfer command or a non-autotransfer command. If the command is a non-autotransfer command, then the sequencer does not proceed directly to the data transfer phase but rather requires microprocessor intervention before proceeding to the data transfer phase. In some embodiments, an autotransfer command (such as an autoread or an autowrite command) is carried out by the disk drive controller integrated circuit with only two interrupts being generated to the microprocessor: one after receiving the autotransfer command from the initiator; and one after data transfer of the autotransfer command is complete. The hard disk controller integrated circuit automatically sends the status byte and command complete message if there is no potential queue tag collision as indicated by a cleared tag not okay flag.

摘要翻译： SCSI目标设备的硬盘控制器集成电路包括定序器，其使SCSI总线在执行自动读取或自动写入SCSI命令期间从命令总线相位转换到数据传输总线相位，而不必等待来自 SCSI目标设备的微处理器。 在一些实施例中，该命令被确定为自动转移命令或非自动转移命令。 如果命令是非自动转换命令，则定序器不会直接进行到数据传输阶段，而是在进行数据传输阶段之前需要微处理器干预。 在一些实施例中，自动转移命令（例如自动读取或自动写入命令）由盘驱动器控制器集成电路执行，其中仅向微处理器生成两个中断：一个在从发起者接收到自动转发命令之后; 并且自动传输命令的数据传输之后完成。 如果没有潜在的队列标签冲突，硬盘控制器集成电路会自动发送状态字节和命令完成消息，如清除标签不正常标志所示。

公开(公告)号：US5603066A

公开(公告)日：1997-02-11

申请号：US463649

申请日：1995-06-05

申请人： Shahe H. Krakirian

发明人： Shahe H. Krakirian

IPC分类号： G06F3/06 ,  G06F13/12 ,  G06F13/38 ,  G06F13/00 ,  G06F13/20

CPC分类号： G06F3/061 ,  G06F13/126 ,  G06F13/385 ,  G06F3/0659 ,  G06F3/0676

摘要： A hard disk controller integrated circuit of a SCSI target device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution of an autoread or an autowrite SCSI command without waiting for a communication from a microprocessor of the SCSI target device. In some embodiments, the command is determined to be either an autotransfer command or a non-autotransfer command. If the command is a non-autotransfer command, then the sequencer does not proceed directly to the data transfer phase but rather requires microprocessor intervention before proceeding to the data transfer phase. In some embodiments, an autotransfer command (such as an autoread or an autowrite command) is carried out by the disk drive controller integrated circuit with only two interrupts being generated to the microprocessor: one after receiving the autotransfer command from the initiator; and one after data transfer of the autotransfer command is complete. The hard disk controller integrated circuit automatically sends the status byte and command complete message if there is no potential queue tag collision as indicated by a cleared tag not okay flag.

摘要翻译： SCSI目标设备的硬盘控制器集成电路包括定序器，其使SCSI总线在执行自动读取或自动写入SCSI命令期间从命令总线相位转换到数据传输总线相位而不等待来自微处理器的通信 的SCSI目标设备。 在一些实施例中，该命令被确定为自动转移命令或非自动转移命令。 如果命令是非自动转换命令，则定序器不会直接进行到数据传输阶段，而是在进行数据传输阶段之前需要微处理器干预。 在一些实施例中，自动转移命令（诸如自动读取或自动写入命令）由盘驱动器控制器集成电路执行，其中只有两个中断被产生到微处理器：一个在从启动器接收到自动转移命令之后; 并且自动传输命令的数据传输之后完成。 如果没有潜在的队列标签冲突，硬盘控制器集成电路会自动发送状态字节和命令完成消息，如清除标签不正常标志所示。

公开(公告)号：US5845154A

公开(公告)日：1998-12-01

申请号：US463333

申请日：1995-06-05

申请人： Shahe H. Krakirian

发明人： Shahe H. Krakirian

IPC分类号： G06F3/06 ,  G06F13/12 ,  G06F13/38 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F3/061 ,  G06F13/126 ,  G06F13/385 ,  G06F3/0659 ,  G06F3/0676

摘要： A hard disk controller integrated circuit of a SCSI target device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution of an autoread or an autowrite SCSI command without waiting for a communication from a microprocessor of the SCSI target device. In some embodiments, the command is determined to be either an autotransfer command or a non-autotransfer command. If the command is a non-autotransfer command, then the sequencer does not proceed directly to the data transfer phase but rather requires microprocessor intervention before proceeding to the data transfer phase. In some embodiments, an autotransfer command (such as an autoread or an autowrite command) is carried out by the disk drive controller integrated circuit with only two interrupts being generated to the microprocessor: one after receiving the autotransfer command from the initiator; and one after data transfer of the autotransfer command is complete. The hard disk controller integrated circuit automatically sends the status byte and command complete message if there is no queue tag collision as indicated by a cleared tag not okay flag.

摘要翻译： SCSI目标设备的硬盘控制器集成电路包括定序器，其使SCSI总线在执行自动读取或自动写入SCSI命令期间从命令总线相位转换到数据传输总线相位而不等待来自微处理器的通信 的SCSI目标设备。 在一些实施例中，该命令被确定为自动转移命令或非自动转移命令。 如果命令是非自动转换命令，则定序器不会直接进行到数据传输阶段，而是在进行数据传输阶段之前需要微处理器干预。 在一些实施例中，自动转移命令（例如自动读取或自动写入命令）由盘驱动器控制器集成电路执行，其中仅向微处理器生成两个中断：一个在从发起者接收到自动转发命令之后; 并且自动传输命令的数据传输之后完成。 如果没有排队标签冲突，硬盘控制器集成电路会自动发送状态字节和命令完成消息，如清除标签不正常标志所示。

公开(公告)号：US5640593A

公开(公告)日：1997-06-17

申请号：US462719

申请日：1995-06-05

申请人： Shahe H. Krakirian

发明人： Shahe H. Krakirian

IPC分类号： G06F3/06 ,  G06F13/12 ,  G06F13/38 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F3/061 ,  G06F13/126 ,  G06F13/385 ,  G06F3/0659 ,  G06F3/0676

摘要： A hard disk controller integrated circuit of a SCSI target device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution of an autoread or an autowrite SCSI command without waiting for a communication from a microprocessor of the SCSI target device. In some embodiments, the command is determined to be either an autotransfer command or a non-autotransfer command. If the command is a non-autotransfer command, then the sequencer does not proceed directly to the data transfer phase but rather requires microprocessor intervention before proceeding to the data transfer phase. In some embodiments, an autotransfer command (such as an autoread or an autowrite command) is carried out by the disk drive controller integrated circuit with only two interrupts being generated to the microprocessor: one after receiving the autotransfer command from the initiator; and one after data transfer of the autotransfer command is complete. The hard disk controller integrated circuit automatically sends the status byte and command complete message if there is no queue tag collision as indicated by a cleared tag not okay flag.

摘要翻译： SCSI目标设备的硬盘控制器集成电路包括定序器，其使SCSI总线在执行自动读取或自动写入SCSI命令期间从命令总线相位转换到数据传输总线相位而不等待来自微处理器的通信 的SCSI目标设备。 在一些实施例中，该命令被确定为自动转移命令或非自动转移命令。 如果命令是非自动转换命令，则定序器不会直接进行到数据传输阶段，而是在进行数据传输阶段之前需要微处理器干预。 在一些实施例中，自动转移命令（诸如自动读取或自动写入命令）由盘驱动器控制器集成电路执行，其中只有两个中断被产生到微处理器：一个在从启动器接收到自动转移命令之后; 并且自动传输命令的数据传输之后完成。 如果没有排队标签冲突，硬盘控制器集成电路会自动发送状态字节和命令完成消息，如清除标签不正常标志所示。

公开(公告)号：US5504868A

公开(公告)日：1996-04-02

申请号：US205003

申请日：1994-03-01

申请人： Shahe H. Krakirian

发明人： Shahe H. Krakirian

IPC分类号： G06F3/06 ,  G06F9/30

CPC分类号： G06F3/0601 ,  G06F2003/0692

摘要： A hard disk controller integrated circuit of a SCSI target device comprises a dedicated command descriptor block "CDB" parsing state machine. The dedicated CDB parsing state machine parses incoming six-byte, ten-byte and twelve-byte SCSI command descriptor blocks and writes information from corresponding fields in the six-byte, ten-byte and twelve-byte SCSI command descriptor blocks into predetermined memory locations. In some embodiments, there are sixteen such predetermined memory locations which together comprise a 16.times.8 register file. A microprocessor coupled to the hard disk controller integrated circuit is therefore relieved of the burden of parsing incoming SCSI command descriptor blocks.

摘要翻译： SCSI目标设备的硬盘控制器集成电路包括专用命令描述符块“CDB”解析状态机。 专用CDB解析状态机解析输入的六字节，十字节和十二字节的SCSI命令描述符块，并将来自六字节，十字节和十二字节的SCSI命令描述符块中的相应字段的信息写入预定的存储器位置 。 在一些实施例中，存在16个这样的预定存储器位置，它们一起包括16×8寄存器文件。 因此，耦合到硬盘控制器集成电路的微处理器解除了传入的SCSI命令描述符块的解析负担。