公开(公告)号：US06909305B1

公开(公告)日：2005-06-21

申请号：US10637840

申请日：2003-08-08

Applicant: Zhongmin Li ,  Troy Ruud ,  Bryce Rasmussen ,  Shan Mo

Inventor： Zhongmin Li ,  Troy Ruud ,  Bryce Rasmussen ,  Shan Mo

IPC: H03K19/00 ,  H03K17/16

CPC classification number: H03K19/0005

Abstract: A digitally controlled impedance driver circuit including a number of fingers, some of which having FETs and series resistors sized in binary or other differential ratios, and some of the higher power FETs being sized in equal ratio and perhaps sharing a series resistor. A DCI controller circuit periodically determines a configuration of the DCI driver circuit that would result in the DCI driver circuit approximating a target impedance. Each time the DCI controller circuit does this, a comparator determines if the impedance of the DCI driver circuit should be increased or decreased. A noise attenuation circuit turns off (or on) only one of the high power fingers if the controller circuit determines that more (or less) impedance is needed even if turning off (or on) only one of the fingers would not result in the configuration of the DCI driver circuit determined by the controller circuit.

Abstract translation: 一种数字控制的阻抗驱动器电路，包括多个指状物，其中一些具有FET和串联电阻器，其尺寸为二进制或其他差分比率，并且一些较高功率FET的大小相等并可能共享串联电阻器。 DCI控制器电路周期性地确定将导致DCI驱动器电路近似目标阻抗的DCI驱动器电路的配置。 每当DCI控制器电路都这样做时，比较器确定是否应该增加或减少DCI驱动电路的阻抗。 如果控制器电路确定需要更多（或更少）的阻抗，即使关闭（或打开）只有一根手指不会导致配置，噪声衰减电路会关闭（或打开）仅一个高功率指针 由控制器电路确定的DCI驱动电路。

公开(公告)号：US07034597B1

公开(公告)日：2006-04-25

申请号：US10933742

申请日：2004-09-03

Applicant: Shan Mo ,  James R. Brown ,  Richard A. Mosher ,  Robert S. Kirk

Inventor： Shan Mo ,  James R. Brown ,  Richard A. Mosher ,  Robert S. Kirk

IPC: H03H11/26

CPC classification number: H04L7/0337 ,  H03L7/0814

Abstract: A dynamic phase adjustment circuit that includes a multi-tap delay line that receives a clock input signal. The multi-tap delay line includes an initial portion that is adjustable, and final portion after the adjustable portion. A number of registers receive the same data. However, the clock signal that causes the registers to sample is received from a corresponding delay element in the final portion of the multi-tap delay line. An edge detect and data decision circuit receives the sampled data values from each of the registers. Sampling resolution is improved over the PLL-based dynamic phase adjustment circuit since the clock signal is delayed using delay elements, which can be made with relatively small delays. Furthermore, the circuit does not contain excessive circuit elements thereby allowing the dynamic phase adjustment circuit to be contained in a small area.

Abstract translation: 一种动态相位调整电路，其包括接收时钟输入信号的多抽头延迟线。 多抽头延迟线包括可调节的初始部分和可调节部分之后的最后部分。 许多寄存器收到相同的数据。 然而，使得寄存器采样的时钟信号从多抽头延迟线的最后部分中的对应延迟元件接收。 边缘检测和数据判定电路从每个寄存器接收采样的数据值。 采样分辨率比基于PLL的动态相位调整电路得到改进，因为时钟信号使用延迟元件进行延迟，延迟元件可以用较小的延迟进行。 此外，电路不包含过多的电路元件，从而允许动态相位调整电路容纳在小的区域中。