公开(公告)号：US07240140B2

公开(公告)日：2007-07-03

申请号：US10796957

申请日：2004-03-11

申请人： Shane L. Bell

发明人： Shane L. Bell

IPC分类号： G06F13/42

CPC分类号： G06F13/4243

摘要： A mechanism detects multiple assertions in a bus efficiently by encoding each of N bus lines with log2(N) pairs of bit lines.

摘要翻译： 一种机制通过用N个总线与N（N）个对（N）位对N总线进行编码来有效地检测总线中的多个断言。

公开(公告)号：US06463548B1

公开(公告)日：2002-10-08

申请号：US09309070

申请日：1999-05-10

申请人： Daniel W. Bailey ,  Jeffrey D. Pickholtz ,  Shane L. Bell

发明人： Daniel W. Bailey ,  Jeffrey D. Pickholtz ,  Shane L. Bell

IPC分类号： G06F104

CPC分类号： G06F1/10

摘要： A method and apparatus are provided for ensuring that a clocked circuit will function after fabrication, regardless of the presence of clock skew. More particularly, a method and apparatus are shown for de-skewing the clock signals of such a clocked circuit only when clock skew is present. When such clock skew does not develop, peak performance of the associated circuit can be achieved by turning off the de-skewing function without removing that functionality from the circuit.

摘要翻译： 提供了一种方法和装置，用于确保时钟电路在制造之后将起作用，而不管时钟偏移的存在。 更具体地，示出了仅当存在时钟偏移时才使用这种时钟电路的时钟信号去偏斜的方法和装置。 当这种时钟偏移不发展时，相关电路的峰值性能可以通过关闭去偏移功能而不从电路中移除该功能来实现。

公开(公告)号：US06925552B2

公开(公告)日：2005-08-02

申请号：US09884675

申请日：2001-06-19

申请人： Matthew H. Reilly ,  Matthew C. Mattina ,  Shane L. Bell ,  Chuan-Hua Chang

发明人： Matthew H. Reilly ,  Matthew C. Mattina ,  Shane L. Bell ,  Chuan-Hua Chang

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3861 ,  G06F9/3842

摘要： An exception handler for a processor is split into two functional units to permit exceptions to be classified into two categories. The first category of exceptions includes performance critical excepted instructions, while the second category includes non-performance critical excepted instructions. The performance critical exceptions are routed to a speculative exception handler, which resolves the exceptions speculatively, even though the excepted instruction may lie in a speculative path of the program flow. The non-performance critical exceptions are routed to a non-speculative exception handler that only resolves exceptions when the excepted instruction is certain to execute in an actual path of the program flow.

摘要翻译： 处理器的异常处理程序分为两个功能单元，以允许将异常分为两类。 第一类异常包括性能关键的除外指令，而第二类包括非性能关键的除外指令。 性能关键异常被路由到推测性的异常处理程序，即异常指令可能位于程序流的推测路径中，该异常处理程序可以推测性地解析异常。 非性能关键异常被路由到非推测性异常处理程序，该异常处理程序仅在排除的指令确定在程序流的实际路径中执行时才解析异常。

公开(公告)号：US06463547B1

公开(公告)日：2002-10-08

申请号：US09457604

申请日：1999-12-08

申请人： Daniel W. Bailey ,  Jeffrey D. Pickholtz ,  Shane L. Bell ,  Richard B. Watson, Jr. ,  William J. Bowhill

发明人： Daniel W. Bailey ,  Jeffrey D. Pickholtz ,  Shane L. Bell ,  Richard B. Watson, Jr. ,  William J. Bowhill

IPC分类号： G06F104

CPC分类号： G06F1/10

摘要： A clock distribution system for a semiconductor device provides for both on-chip and in-package clock distribution via on-chip and in-package clock distribution networks. Each of these networks is selectively enabled depending on the mode of operation. Specifically, for wafer testing, the on-chip clock distribution network is selected. Thus, a probe tester need only provide a single clock source with conventional timing specifications to test the operation of the chip. In contrast, during normal operation, an in-package clock distribution network is enabled. In-package clock routing provides the lowest variation mode and thus, will result in the maximum clock frequency for the chip.

摘要翻译： 用于半导体器件的时钟分配系统通过片上和封装内时钟分配网络提供片内和封装内时钟分配。 这些网络中的每一个根据操作模式被选择性地启用。 具体来说，对于晶片测试，选择片上时钟分配网络。 因此，探头测试器仅需要提供具有常规时序规格的单个时钟源来测试芯片的操作。 相比之下，在正常操作期间，启用了一体式的时钟分配网络。 包内时钟路由提供最低的变化模式，因此将导致芯片的最大时钟频率。

公开(公告)号：US07240186B2

公开(公告)日：2007-07-03

申请号：US09906345

申请日：2001-07-16

申请人： Shane L. Bell ,  Matthew C. Mattina

发明人： Shane L. Bell ,  Matthew C. Mattina

IPC分类号： G06F9/44

CPC分类号： G06F9/3861 ,  G06F9/3851

摘要： A multi-threaded processor is configured to detect excepted instructions from a first program, and to stop fetching younger instructions from that same program, to thereby conserve system resources that can be used by other programs. Each fetched program instruction has an associated status bit, which is set if the instruction excepts. Each excepting instruction is logged in an exception logging unit, which causes the associated status bit to be set. Each program has an associated in-flight vector table that tracks the instructions that have been fetched for that program. The status bits are compared with the in-flight vector table to identify the program that is associated with an excepted instruction. That program is then disabled, thereby preventing further fetching of instructions for that program until the excepted instruction clears.

摘要翻译： 多线程处理器被配置为检测来自第一程序的除外指令，并且停止从该同一程序获取较年轻的指令，从而节省可由其他程序使用的系统资源。 每个获取的程序指令都有一个关联的状态位，如果指令除外，则该位被置位。 每个除了指令都记录在异常记录单元中，这会导致相关的状态位被置位。 每个程序都有一个关联的飞行中向量表，跟踪已经为该程序获取的指令。 将状态位与飞行中矢量表进行比较，以识别与异常指令相关联的程序。 然后该程序被禁用，从而防止进一步获取该程序的指令，直到除外的指令清除为止。