公开(公告)号：US20120182818A1

公开(公告)日：2012-07-19

申请号：US13006487

申请日：2011-01-14

Applicant: Yi-Cheng Huang ,  Shang-Hsuan Liu ,  Yuan-Long Siao

Inventor： Yi-Cheng Huang ,  Shang-Hsuan Liu ,  Yuan-Long Siao

IPC: G11C7/12

CPC classification number: G11C7/067 ,  G11C7/12 ,  G11C16/26 ,  G11C16/28

Abstract: A sense amplifier circuit includes a precharge circuit configured to precharge a bit line coupled to a sensing node in response to a precharge control signal and a sense output circuit. The sense output circuit includes a sense output inverter coupled to the sensing node. The sense output inverter is disabled during bit line precharging and for a period after bit line precharging is complete, and thereafter the sense output inverter is enabled.

Abstract translation: 读出放大器电路包括预充电电路，其被配置为响应于预充电控制信号和感测输出电路对耦合到感测节点的位线进行预充电。 感测输出电路包括耦合到感测节点的感测输出反相器。 在位线预充电期间和位线预充电完成后的一段时间内，感测输出逆变器被禁止，此后，感测输出反相器被使能。

公开(公告)号：US07202899B2

公开(公告)日：2007-04-10

申请号：US10152469

申请日：2002-05-21

Applicant: Kuen-Hsien Lin ,  Shang-Hsuan Liu ,  Chih-Hsing Chen ,  Hung Jen Tsai ,  Hsien-Tsong Liu

Inventor： Kuen-Hsien Lin ,  Shang-Hsuan Liu ,  Chih-Hsing Chen ,  Hung Jen Tsai ,  Hsien-Tsong Liu

IPC: H04N3/14

CPC classification number: H01L27/14687 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14643

Abstract: A method and system for preventing white pixel difficulties resulting from undesired current induced in an image sensor having a photodiode and a depletion region therein. The photodiode is isolated in a pixel layout for an image sensor. A depletion region is configured, such that the depletion region is maintained in a defect-free region associated with the pixel layout for the image sensor, thereby reducing white pixel difficulties caused by induced and undesired current. The image sensor is preferably a CMOS image sensor. A depletion region of the photodiode is constantly maintained in a defect-free region during operation of the CMOS image sensor.

Abstract translation: 一种用于防止由于在其中具有光电二极管和耗尽区域的图像传感器中感应出不期望的电流导致的白色像素困难的方法和系统。 在图像传感器的像素布局中隔离光电二极管。 耗尽区域被配置为使得耗尽区域保持在与图像传感器的像素布局相关联的无缺陷区域中，从而减少由感应和不期望的电流引起的白色像素困难。 图像传感器优选为CMOS图像传感器。 在CMOS图像传感器的操作期间，光电二极管的耗尽区域始终保持在无缺陷区域中。

公开(公告)号：US20070041244A1

公开(公告)日：2007-02-22

申请号：US11204477

申请日：2005-08-16

Applicant: Yue-Der Chih ,  Shang-Hsuan Liu

Inventor： Yue-Der Chih ,  Shang-Hsuan Liu

IPC: G11C16/04

CPC classification number: G11C16/24 ,  G11C16/12 ,  G11C16/3427

Abstract: A method and system is disclosed for prohibiting program disturbance in a memory array device. The system comprises a bit-line decoder coupled to each bit-line of the memory array for providing a predetermined current diverting path, a biased resistance module placed on the bit-line of the flash memory array through which a pull-up current provided by a predetermined power supply is diverted by the bit-line decoder when a cell of the flash memory array connecting to the bit-line is programmed. The programming current of the cell of the flash memory array is stabilized due to the diverted pull-up current.

Abstract translation: 公开了一种用于禁止存储器阵列器件中的程序干扰的方法和系统。 该系统包括耦合到存储器阵列的每个位线的位线解码器，用于提供预定的电流转向路径，位于闪速存储器阵列的位线上的偏置电阻模块，通过该位线线提供上拉电流 当连接到位线的闪速存储器阵列的单元被编程时，位线解码器转移预定的电源。 闪存阵列的单元的编程电流由于转向上拉电流而稳定。

公开(公告)号：US20120275249A1

公开(公告)日：2012-11-01

申请号：US13543571

申请日：2012-07-06

Applicant: Tien-Chun YANG ,  Yue-Der CHIH ,  Shang-Hsuan LIU

Inventor： Tien-Chun YANG ,  Yue-Der CHIH ,  Shang-Hsuan LIU

IPC: G11C29/00

CPC classification number: G11C29/04 ,  G11C16/0408 ,  G11C16/0483 ,  G11C29/808

Abstract: A memory circuit includes a group of memory arrays and at least one redundancy bit line. The group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. The at least one redundancy bit line is configured to selectively repair the group of memory arrays.

Abstract translation: 存储器电路包括一组存储器阵列和至少一个冗余位线。 该组存储器阵列包括与第一输入/输出（IO）接口耦合的第一存储器阵列和与第二IO接口耦合的第二存储器阵列。 至少一个冗余位线被配置为选择性地修复该组存储器阵列。

公开(公告)号：US08238178B2

公开(公告)日：2012-08-07

申请号：US12704676

申请日：2010-02-12

Applicant: Tien-Chun Yang ,  Yue-Der Chih ,  Shang-Hsuan Liu

Inventor： Tien-Chun Yang ,  Yue-Der Chih ,  Shang-Hsuan Liu

IPC: G11C7/00 ,  G11C11/34

CPC classification number: G11C29/04 ,  G11C16/0408 ,  G11C16/0483 ,  G11C29/808

Abstract: A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third IO interface and a fourth memory array coupled with a fourth TO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays.

Abstract translation: 存储器电路包括第一组存储器阵列，其包括与第一输入/输出（IO）接口耦合的第一存储器阵列和与第二IO接口耦合的第二存储器阵列。 第二组存储器阵列包括与第三IO接口耦合的第三存储器阵列和与第四TO接口耦合的第四存储器阵列。 多个冗余位线包括被配置用于选择性地修复第一组存储器阵列的至少一个第一冗余位线和被配置用于选择性地修复第二组存储器阵列的至少一个第二冗余位线。

公开(公告)号：US20110199845A1

公开(公告)日：2011-08-18

申请号：US12704676

申请日：2010-02-12

Applicant: Tien-Chun YANG ,  Yue-Der Chih ,  Shang-Hsuan Liu

Inventor： Tien-Chun YANG ,  Yue-Der Chih ,  Shang-Hsuan Liu

IPC: G11C29/00

CPC classification number: G11C29/04 ,  G11C16/0408 ,  G11C16/0483 ,  G11C29/808

Abstract: A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third input/output (IO) interface and a fourth memory array coupled with a fourth IO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays.

Abstract translation: 存储器电路包括第一组存储器阵列，其包括与第一输入/输出（IO）接口耦合的第一存储器阵列和与第二IO接口耦合的第二存储器阵列。 第二组存储器阵列包括与第三输入/输出（IO）接口耦合的第三存储器阵列和与第四IO接口耦合的第四存储器阵列。 多个冗余位线包括被配置用于选择性地修复第一组存储器阵列的至少一个第一冗余位线和被配置用于选择性地修复第二组存储器阵列的至少一个第二冗余位线。

公开(公告)号：US07215583B2

公开(公告)日：2007-05-08

申请号：US11204477

申请日：2005-08-16

Applicant: Yue-Der Chih ,  Shang-Hsuan Liu

Inventor： Yue-Der Chih ,  Shang-Hsuan Liu

IPC: G11C7/00

CPC classification number: G11C16/24 ,  G11C16/12 ,  G11C16/3427

Abstract: A method and system is disclosed for prohibiting program disturbance in a memory array device. The system comprises a bit-line decoder coupled to each bit-line of the memory array for providing a predetermined current diverting path, a biased resistance module placed on the bit-line of the flash memory array through which a pull-up current provided by a predetermined power supply is diverted by the bit-line decoder when a cell of the flash memory array connecting to the bit-line is programmed. The programming current of the cell of the flash memory array is stabilized due to the diverted pull-up current.

公开(公告)号：US08670282B2

公开(公告)日：2014-03-11

申请号：US13543571

申请日：2012-07-06

Applicant: Tien-Chun Yang ,  Yue-Der Chih ,  Shang-Hsuan Liu

Inventor： Tien-Chun Yang ,  Yue-Der Chih ,  Shang-Hsuan Liu

IPC: G11C29/00 ,  G11C11/34

CPC classification number: G11C29/04 ,  G11C16/0408 ,  G11C16/0483 ,  G11C29/808

Abstract: A memory circuit includes a group of memory arrays and at least one redundancy bit line. The group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. The at least one redundancy bit line is configured to selectively repair the group of memory arrays.

Abstract translation: 存储器电路包括一组存储器阵列和至少一个冗余位线。 该组存储器阵列包括与第一输入/输出（IO）接口耦合的第一存储器阵列和与第二IO接口耦合的第二存储器阵列。 至少一个冗余位线被配置为选择性地修复该组存储器阵列。

公开(公告)号：US08339884B2

公开(公告)日：2012-12-25

申请号：US13006487

申请日：2011-01-14

Applicant: Yi-Cheng Huang ,  Shang-Hsuan Liu ,  Yuan-Long Siao

Inventor： Yi-Cheng Huang ,  Shang-Hsuan Liu ,  Yuan-Long Siao

IPC: G11C7/00

CPC classification number: G11C7/067 ,  G11C7/12 ,  G11C16/26 ,  G11C16/28

Abstract: A sense amplifier circuit includes a precharge circuit configured to precharge a bit line coupled to a sensing node in response to a precharge control signal and a sense output circuit. The sense output circuit includes a sense output inverter coupled to the sensing node. The sense output inverter is disabled during bit line precharging and for a period after bit line precharging is complete, and thereafter the sense output inverter is enabled.

Abstract translation: 读出放大器电路包括预充电电路，其被配置为响应于预充电控制信号和感测输出电路对耦合到感测节点的位线进行预充电。 感测输出电路包括耦合到感测节点的感测输出反相器。 在位线预充电期间和位线预充电完成后的一段时间内，感测输出逆变器被禁止，此后，感测输出反相器被使能。