公开(公告)号：US06387757B1

公开(公告)日：2002-05-14

申请号：US09761912

申请日：2001-01-17

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Jake Yeh ,  Chia-Da Hsieh ,  Chuan-Li Chang ,  Sheng-Wei Tsaur

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Jake Yeh ,  Chia-Da Hsieh ,  Chuan-Li Chang ,  Sheng-Wei Tsaur

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Within a method for fabricating a split gate field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication, there is employed a sacrificial self aligned spacer layer which defines a control gate electrode channel within the split gate field effect transistor (FET). The sacrificial self aligned spacer layer is employed as part of an ion implantation mask employed for forming a source/drain region adjoining the control gate electrode channel within the split gate field effect transistor (FET). The sacrificial self aligned spacer layer is stripped from over the control gate electrode channel prior to forming over the control gate electrode channel a control gate electrode within the split gate field effect transistor.

摘要翻译： 在用于在半导体集成电路微电子制造中制造分裂栅极场效应晶体管（FET）的方法中，采用限定分裂栅极场效应晶体管（FET）内的控制栅电极通道的牺牲自对准间隔层。 牺牲自对准间隔层被用作用于形成与分离栅场效应晶体管（FET）内的控制栅电极通道相邻的源/漏区的离子注入掩模的一部分。 在控制栅电极通道上形成分割栅场效应晶体管内的控制栅极电极之前，将牺牲自对准间隔层从控制栅电极通道上剥离。

公开(公告)号：US06544828B1

公开(公告)日：2003-04-08

申请号：US10044860

申请日：2001-11-07

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Jack Yeh ,  Chia-Ta Hsieh ,  Chrong-Jung Lin ,  Sheng-Wei Tsaur

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Jack Yeh ,  Chia-Ta Hsieh ,  Chrong-Jung Lin ,  Sheng-Wei Tsaur

IPC分类号： H01L218234

CPC分类号： H01L29/402 ,  H01L21/28123 ,  H01L21/823481 ,  H01L29/4238

摘要： A method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of a shallow trench isolation region at the drain side only is described. Active areas are separated by isolation regions in a substrate. A gate oxide layer is grown on the active areas. A conducting layer is deposited overlying the gate oxide layer and patterned to form gate electrodes in the active areas and to form conductive strips overlapping both the active areas and the isolation areas at an isolation's edge on a drain side of the active areas wherein the conductive strips reduce the electric field at the isolation's edge in the fabrication of an integrated circuit device.

摘要翻译： 描述了通过在漏极侧的浅沟槽隔离区域的边缘处形成导电场板来提高高电压NMOS器件的耐久性和鲁棒性的方法。 活性区域通过衬底中的隔离区域分离。 在活性区域上生长栅极氧化物层。 导电层沉积在栅极氧化物层上并被图案化以在有源区域中形成栅电极，并且在有源区域的漏极侧上的隔离边缘处形成与有源区域和隔离区域重叠的导电条带，其中导电条 在集成电路器件的制造中减小隔离边缘的电场。

公开(公告)号：US06468863B2

公开(公告)日：2002-10-22

申请号：US09761276

申请日：2001-01-16

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chuan-Li Chang ,  Wen-Ting Chu ,  Sheng-Wei Tsaur

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chuan-Li Chang ,  Wen-Ting Chu ,  Sheng-Wei Tsaur

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： Within both a method for fabricating a split gate field effect transistor and the split gate field effect transistor fabricated employing the method, there is employed a patterned silicon nitride barrier dielectric layer formed covering a first portion of a floating gate and a first portion of a semiconductor substrate adjacent the first portion of the floating gate. Within the first portion of the semiconductor substrate there is eventually formed a source/drain region, and more particularly a source region, when fabricating the split gate field effect transistor. The patterned silicon nitride barrier dielectric layer inhibits when fabricating the split gate field effect transistor ion implant damage of the floating gate and oxidative loss of a floating gate electrode edge.

摘要翻译： 在制造分裂栅极场效应晶体管的方法和使用该方法制造的分裂栅极场效应晶体管的两者中，采用形成为覆盖浮置栅极的第一部分和半导体的第一部分的图案化氮化硅阻挡介电层 衬底邻近浮动栅极的第一部分。 在半导体衬底的第一部分内，当制造分裂栅极场效应晶体管时，最终形成源极/漏极区域，尤其是源极区域。 图案化的氮化硅阻挡介电层在制造分离栅场效应晶体管离子注入损坏浮栅和浮栅电极边缘的氧化损失时禁止。