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公开(公告)号：US20140042523A1
公开(公告)日：2014-02-13
申请号：US14112097
申请日：2012-02-24
IPC分类号： H01L29/78
CPC分类号： H01L29/7801 , H01L27/0629 , H01L29/0623 , H01L29/1608 , H01L29/165 , H01L29/41766 , H01L29/4238 , H01L29/66068 , H01L29/7803 , H01L29/7805 , H01L29/7806 , H01L29/7813
摘要： An anode region 106 is formed on a bottom portion of a trench 105 in which a gate electrode 108 is formed or in a drift region 102 immediately under the trench 105. A contact hole 110 is formed in the trench 105 at a depth reaching the anode region 106. A source electrode 112 is embedded in the contact hole 110 while interposing an inner wall insulating film 111 therebetween. The anode region 106 and the source electrode 112 are electrically connected to each other in a state of being insulated from the gate electrode 108 by the inner wall insulating film 111.
摘要翻译： 阳极区域106形成在其中形成有栅电极108的沟槽105的底部或沟槽105正下方的漂移区域102中。接触孔110在到达阳极的深度处形成在沟槽105中 源电极112嵌入在接触孔110中，同时在其间插入内壁绝缘膜111。 阳极区域106和源极电极112通过内壁绝缘膜111与栅电极108绝缘的状态彼此电连接。
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公开(公告)号：US07880199B2
公开(公告)日：2011-02-01
申请号：US11790791
申请日：2007-04-27
IPC分类号： H01L29/66
CPC分类号： H01L29/0847 , H01L29/1033 , H01L29/1608 , H01L29/267 , H01L29/4916 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device is provided with: a semiconductor substrate of a predetermined electroconduction type; a hetero semiconductor region contacted with a first main surface of the semiconductor substrate and comprising a semiconductor material having a bandgap different from that of the semiconductor substrate; a gate electrode formed through a gate insulator layer at a position adjacent to a junction region between the hetero semiconductor region and the semiconductor substrate; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor substrate; wherein the hetero semiconductor region includes a contact portion contacted with the source electrode, at least a partial region of the contact portion is of the same electroconduction type as the electroconduction type of the semiconductor substrate, and the partial region has an impurity concentration higher than an impurity concentration of at least that partial region of a gate-electrode facing portion in the hetero semiconductor region which is positioned to face toward the gate electrode through the gate insulator layer.
摘要翻译： 半导体器件具有：预定的导电型的半导体衬底; 与所述半导体衬底的第一主表面接触并且包括具有与所述半导体衬底的带隙不同的带隙的半导体材料的异质半导体区域; 在与所述异质半导体区域和所述半导体基板之间的接合区域相邻的位置处形成的栅极电极， 连接到所述异质半导体区的源电极; 和连接到半导体衬底的漏电极; 其中所述异质半导体区域包括与所述源电极接触的接触部分，所述接触部分的至少一部分区域具有与所述半导体衬底的导电型相同的导电类型，并且所述部分区域的杂质浓度高于 至少通过栅极绝缘体层位于面向栅电极的异质半导体区域中的栅电极面对部分的部分区域的杂质浓度。
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公开(公告)号：US07859015B2
公开(公告)日：2010-12-28
申请号：US12423207
申请日：2009-04-14
IPC分类号： H01L31/072
CPC分类号： H01L29/78 , H01L21/047 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： A semiconductor device is provided with a semiconductor region, a gate electrode, a source electrode and a drain electrode. The semiconductor region is formed on a semiconductor substrate surface and includes a first semiconductor portion of a first conducting type, a second semiconductor portion of a second conducting type, a band gap distinct from the substrate's band gap, more than two accumulated semiconductor layers, and junctions between the layers. The semiconductor layers each contain an impurity of the first conducting type. The gate electrode adjoins a heterojunction between the second semiconductor portion and the semiconductor substrate through a gate insulation film. The source electrode is coupled to the semiconductor region. The drain electrode is coupled to the semiconductor substrate.
摘要翻译： 半导体器件设置有半导体区域，栅极电极，源极电极和漏极电极。 半导体区域形成在半导体衬底表面上，并且包括第一导电类型的第一半导体部分，第二导电类型的第二半导体部分，与衬底带隙不同的带隙，多于两个的累积半导体层，以及 层之间的交叉点。 半导体层各自含有第一导电类型的杂质。 栅极通过栅极绝缘膜与第二半导体部分和半导体衬底之间的异质结相邻。 源电极耦合到半导体区域。 漏电极耦合到半导体衬底。
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公开(公告)号：US07781802B2
公开(公告)日：2010-08-24
申请号：US11790679
申请日：2007-04-26
IPC分类号： H01L21/4763
CPC分类号： H01L29/8613 , H01L21/0465 , H01L21/0475 , H01L29/0615 , H01L29/1608 , H01L29/267 , H01L29/6606 , H01L29/66136
摘要： As semiconductor regions in contact with a first main surface of a semiconductor base composed by forming an N− silicon carbide epitaxial layer on an N+ silicon carbide substrate connected to a cathode electrode, there are provided both of an N+ polycrystalline silicon layer of a same conduction type as a conduction type of the semiconductor base and a P+ polycrystalline silicon layer of a conduction type different from the conduction type of the semiconductor base. Both of the N+ polycrystalline silicon layer and the P+ polycrystalline silicon layer are hetero-joined to the semiconductor base, and are ohmically connected to the anode electrode. Moreover, the N+ polycrystalline silicon layer of the same conduction type as the conduction type of the semiconductor base is formed so as to contact the first main surface of the semiconductor base, and the P+ polycrystalline silicon layer of the conduction type different from the conduction type of the semiconductor base is formed in trenches dug on the first main surface of the semiconductor base.
摘要翻译： 作为与通过在与阴极连接的N +碳化硅衬底上形成N-碳化硅外延层而构成的半导体衬底的第一主表面接触的半导体区域，提供了具有相同导电性的N +多晶硅层 类型为半导体基底的导电类型和不同于半导体基底的导电类型的导电类型的P +多晶硅层。 N +多晶硅层和P +多晶硅层都与半导体基体异相接合，并与欧姆连接到阳极电极。 此外，形成与半导体基底的导电类型相同的导电类型的N +多晶硅层，以便与半导体基底的第一主表面接触，并且与导电类型不同的导电类型的P +多晶硅层 形成在半导体基底的第一主表面上的沟槽中。
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公开(公告)号：US07714352B2
公开(公告)日：2010-05-11
申请号：US11701429
申请日：2007-02-02
IPC分类号： H01L31/0312 , H01L31/036 , H01L29/10 , H01L29/93
CPC分类号： H01L29/267 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device, includes: a first conductivity-semiconductor substrate; a hetero semiconductor region for forming a hetero junction with the first conductivity-semiconductor substrate; a gate electrode adjacent to a part of the hetero junction by way of a gate insulating film; a drain electrode connecting to the first conductivity-semiconductor substrate; a source electrode connecting to the hetero semiconductor region; and a second conductivity-semiconductor region formed on a part of a first face of the first conductivity-semiconductor substrate in such a configuration as to oppose the gate electrode via the gate insulating film, the gate insulating film, the hetero semiconductor region and the first conductivity-semiconductor substrate contacting each other to thereby form a triple contact point. A first face of the second conductivity-semiconductor region has such an impurity concentration that allows a field from the gate electrode to form an inversion layer on the first face of the second conductivity-semiconductor region.
摘要翻译： 一种半导体器件，包括：第一导电半导体衬底; 用于与第一导电半导体衬底形成异质结的异质半导体区域; 通过栅绝缘膜与所述异质结的一部分相邻的栅电极; 连接到所述第一导电半导体衬底的漏电极; 连接到所述异质半导体区域的源电极; 以及第二导电半导体区域，形成在第一导电半导体基板的第一面的一部分上，以与栅电极相对的方式经由栅极绝缘膜，栅极绝缘膜，异质半导体区域和第一导电半导体区域 导电性半导体基板彼此接触，从而形成三重接触点。 第二导电率半导体区域的第一面具有允许来自栅电极的场在第二导电半导体区域的第一面上形成反型层的杂质浓度。
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公开(公告)号：US07695997B2
公开(公告)日：2010-04-13
申请号：US11790792
申请日：2007-04-27
IPC分类号： H01L21/00 , H01L31/072
CPC分类号： H01L27/0255 , H01L28/20 , H01L29/1608 , H01L29/161 , H01L29/267 , H01L29/66068 , H01L29/7828 , H01L29/866
摘要： An electrostatic discharge protection element and a protection resistor, which are formed on an N− drain region with a field oxide film interposed therebetween for the purpose of preventing electrical breakdown of a field effect transistor, are composed as a stacked bidirectional Zener diode of one or a plurality of N+ polycrystalline silicon regions of a first layer and a P+ polycrystalline silicon region of a second layer, and a stacked resistor of one or a plurality of N+ resistor layers of the first layer and an N+ resistor layer of the second layer, respectively. One end of the plurality of N+ polycrystalline silicon regions of the first layer is connected to an external gate electrode terminal, and the other end is connected to a source electrode. One end of the plurality of N+ resistor layers of the first layer is connected to a gate electrode, and the other end is connected to the external gate electrode terminal. Semiconductor regions of the first layer and the second layer are formed by using semiconductor films, which form a hetero semiconductor region and the gate electrode, respectively.
摘要翻译： 为了防止场效应晶体管的电击穿而形成在其上具有场氧化物膜的N-漏极区域上的静电放电保护元件和保护电阻器被构成为一个或多个二极管的叠层双向齐纳二极管， 第一层的多个N +多晶硅区域和第二层的P +多晶硅区域，以及第一层的一个或多个N +电阻层和第二层的N +电阻层的层叠电阻器 。 第一层的多个N +多晶硅区域的一端连接到外部栅电极端子，另一端与源电极连接。 第一层的多个N +电阻层的一端连接到栅电极，另一端连接到外部栅电极端子。 通过使用分别形成杂半导体区域和栅电极的半导体膜来形成第一层和第二层的半导体区域。
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公开(公告)号：US07642149B2
公开(公告)日：2010-01-05
申请号：US11907401
申请日：2007-10-11
IPC分类号： H01L21/8238
CPC分类号： H01L29/267 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A method for producing a semiconductor device which includes: a semiconductor base, a hetero semiconductor region made of a semiconductor material different in band gap from a semiconductor material for the semiconductor base, and so configured as to form a hetero junction in combination with the semiconductor base, a gate insulating film so configured as to contact with the hetero junction between the semiconductor base and the hetero semiconductor region, a gate electrode so configured as to contact with the gate insulating film, a source electrode connected to the hetero semiconductor region, and a drain electrode connected to the semiconductor base. The method includes: forming the following in a self-aligning manner, by using a certain mask material: a source contact hole for the source electrode, and the gate electrode.
摘要翻译： 一种半导体器件的制造方法，其特征在于，包括：半导体基底，与半导体基板的半导体材料的带隙不同的半导体材料构成的异质半导体区域，与半导体基板结合形成异质结 基底，被配置为与半导体基底和异质半导体区域之间的异质结接触的栅极绝缘膜，被配置为与栅极绝缘膜接触的栅极电极，连接到异质半导体区域的源极电极，以及 连接到半导体基底的漏电极。 该方法包括：通过使用某种掩模材料：源电极的源极接触孔和栅电极，以自对准的方式形成以下。
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公开(公告)号：US20090267113A1
公开(公告)日：2009-10-29
申请号：US12066145
申请日：2006-08-02
IPC分类号： H01L29/267 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/0445 , H01L29/0696 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device has a semiconductor base of a first conductivity type; a hetero semiconductor region in contact with the semiconductor base; a gate electrode adjacent to a portion of a junction between the hetero semiconductor region and the semiconductor base across a gate insulating film; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor base. The hetero semiconductor region has a band gap different from that of the semi-conductor base. The hetero semiconductor region includes a first hetero semiconductor region and a second hetero semiconductor region. The first hetero semiconductor region is formed before the gate insulating film is formed. The second hetero semiconductor region is formed after the gate insulating film is formed.
摘要翻译： 半导体器件具有第一导电类型的半导体基底; 与半导体基底接触的异质半导体区域; 与栅极绝缘膜相邻的异质半导体区域和半导体基底之间的结的部分相邻的栅电极; 连接到所述异质半导体区的源电极; 以及连接到半导体基底的漏电极。 异质半导体区域具有与半导体基底不同的带隙。 异质半导体区域包括第一异质半导体区域和第二异质半导体区域。 在形成栅极绝缘膜之前形成第一异质半导体区域。 在形成栅极绝缘膜之后形成第二异质半导体区域。
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公开(公告)号：US20090026497A1
公开(公告)日：2009-01-29
申请号：US11988305
申请日：2006-06-26
申请人： Yoshio Shimoida , Hideaki Tanaka , Tetsuya Hayashi , Masakatsu Hoshi , Shigeharu Yamagami , Noriaki Kawamoto , Takayuki Kitou , Mineo Miura , Takashi Nakamura
发明人： Yoshio Shimoida , Hideaki Tanaka , Tetsuya Hayashi , Masakatsu Hoshi , Shigeharu Yamagami , Noriaki Kawamoto , Takayuki Kitou , Mineo Miura , Takashi Nakamura
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/049 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： A method for producing a semiconductor device (20) is disclosed. The semiconductor device (20) includes: 1) a semiconductor substrate (1, 2), 2) a hetero semiconductor area (3) configured to contact a first main face (1A) of the semiconductor substrate (1, 2) and different from the semiconductor substrate (1, 2) in band gap, 3) a gate electrode (7) contacting, via a gate insulating film (6), a part of a junction part (13) between the hetero semiconductor area (3) and the semiconductor substrate (1, 2), 4) a source electrode (8) configured to connect to the hetero semiconductor area (3), and 5) a drain electrode (9) configured to make an ohmic connection with the semiconductor substrate (1, 2). The method includes the following sequential operations: i) forming the gate insulating film (6); and ii) nitriding the gate insulating film (6).
摘要翻译： 公开了一种用于制造半导体器件（20）的方法。 半导体器件（20）包括：1）半导体衬底（1,2），2）异质半导体区域（3），被配置为接触半导体衬底（1,2）的第一主面（1A） 所述半导体衬底（1,2）具有带隙，3）栅极电极（7）经由栅极绝缘膜（6）与所述异质半导体区域（3）之间的接合部分（13）的一部分 半导体衬底（1,2），4）构造成连接到所述异质半导体区域（3）的源电极（8），以及5）被配置为与所述半导体衬底（1,2）形成欧姆连接的漏电极（9） 2）。 该方法包括以下顺序操作：i）形成栅极绝缘膜（6）; 和ii）氮化所述栅极绝缘膜（6）。
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10.发明申请METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREFROM 有权制造半导体器件的方法及其制造的半导体器件公开(公告)号：US20080203401A1
公开(公告)日：2008-08-28
申请号：US12033468
申请日：2008-02-19
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7828
摘要： A method for producing a semiconductor device includes forming a first hetero-semiconductor layer as a hetero-junction to a surface of a silicon carbide epitaxial layer. This layer is composed of polycrystalline silicon having a band gap different from that of the silicon carbide epitaxial layer. An etching stopper layer composed of a material having a different etching rate from that of the polycrystalline silicon is formed on the surface of the first hetero-semiconductor layer. A second hetero-semiconductor layer composed of polycrystalline silicon is formed so that the second hetero-semiconductor layer contacts the surface of the first hetero-semiconductor layer and the etching stopper layer. The etching stopper layer is removed, the first hetero-semiconductor layer is thermally oxidized, and the thermally oxidized portion is then removed.
摘要翻译： 一种制造半导体器件的方法包括：将第一异质半导体层形成为与碳化硅外延层的表面的异质结。 该层由具有与碳化硅外延层的带隙不同的带隙的多晶硅构成。 在第一异质半导体层的表面上形成由具有与多晶硅的蚀刻速率不同的蚀刻速率的材料构成的蚀刻停止层。 形成由多晶硅构成的第二异质半导体层，使得第二异质半导体层与第一异质半导体层和蚀刻停止层的表面接触。 除去蚀刻停止层，将第一异质半导体层热氧化，然后除去热氧化部分。
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