公开(公告)号：US11996362B2

公开(公告)日：2024-05-28

申请号：US17493715

申请日：2021-10-04

申请人： Intel Corporation

发明人： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru ,  Ranjith Kumar

IPC分类号： H01L23/528 ,  G06F30/392 ,  G06F30/394 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/772 ,  H01L29/78

CPC分类号： H01L23/528 ,  G06F30/392 ,  G06F30/394 ,  H01L21/30604 ,  H01L21/768 ,  H01L21/76898 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/785 ,  H01L29/7851

摘要： Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.

公开(公告)号：US09911598B2

公开(公告)日：2018-03-06

申请号：US15404955

申请日：2017-01-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Mohit Bajaj ,  Suresh Gundapaneni ,  Aniruddha Konar ,  Narasimha R. Mavilla ,  Kota V. R. M. Murali ,  Edward J. Nowak

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/24 ,  H01L29/161 ,  H01L29/205 ,  H01L29/78 ,  H01L29/772

CPC分类号： H01L29/41725 ,  H01L21/02414 ,  H01L21/02483 ,  H01L21/02565 ,  H01L21/02581 ,  H01L21/3115 ,  H01L21/8232 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/205 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/772 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78693

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.

公开(公告)号：US09806203B2

公开(公告)日：2017-10-31

申请号：US15178391

申请日：2016-06-09

申请人： Intel Corporation

发明人： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Robert S. Chau

IPC分类号： H01L29/20 ,  H01L29/78 ,  H01L29/786 ,  H01L29/772 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/04 ,  H01L29/06 ,  H01L29/205

CPC分类号： H01L29/78696 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/02538 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66409 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78681

摘要： A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

公开(公告)号：US20170278944A1

公开(公告)日：2017-09-28

申请号：US15503989

申请日：2014-09-19

申请人： Intel Corporation

发明人： Chandra S. Mohapatra ,  Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Willy Rachmady ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC分类号： H01L29/66 ,  H01L29/772 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/775

CPC分类号： H01L29/66469 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7851

摘要： Transistor devices having a doped buffer or sub-structure between an active channel and a substrate. In one embodiment, a p-type dopant, such as magnesium, zinc, carbon, beryllium, and the like, may be introduced in the formation of the sub-structure, wherein the dopant may act as a p/n junction at the active channel to source and drain interfaces and decrease the off-state leakage path. In another embodiment, the material used for the formation of the doped sub-structure may be substantially the same as the material, without the dopant, used for the formation of the active channel, such that no heterojunction will be formed which could result in crystalline imperfections.

公开(公告)号：US20170264184A1

公开(公告)日：2017-09-14

申请号：US15608582

申请日：2017-05-30

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shinichi TEZUKA ,  Hidetomo OHASHI

IPC分类号： H02M1/084 ,  H03K17/0812 ,  H01L29/78 ,  H03K17/687 ,  H01L29/06 ,  H01L29/772 ,  H02M7/48 ,  G11C11/4091

CPC分类号： H02M1/084 ,  G11C11/4091 ,  G11C2211/4013 ,  H01L29/0603 ,  H01L29/772 ,  H01L29/7802 ,  H02M1/32 ,  H02M7/48 ,  H02M7/5387 ,  H03K17/08122 ,  H03K17/0822 ,  H03K17/687 ,  H03K2217/0063 ,  H03K2217/0072

摘要： In a semiconductor device, a high-side potential determination circuit outputs an event signal when a high-side reference potential detected by a high-side potential detection circuit rises. If at that time an input logic signal for controlling a high side is at a low (L) level, a pulse generation circuit regenerates a reset signal for a high-side drive circuit. When the input logic signal for controlling the high side is at the L level and the event signal is inputted, an overcurrent detection determination circuit makes an overcurrent detection signal from an overcurrent detection circuit invalid. When the event signal is not inputted, the overcurrent detection determination circuit makes the overcurrent detection signal valid.

公开(公告)号：US09659840B2

公开(公告)日：2017-05-23

申请号：US14186360

申请日：2014-02-21

申请人： GLOBALFOUNDRIES Inc.

发明人： Christian Klewer

IPC分类号： H01L21/76 ,  H01L23/48 ,  H01L21/768 ,  H01L29/772

CPC分类号： H01L23/481 ,  H01L21/76801 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/53238 ,  H01L29/0649 ,  H01L29/772 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed. Embodiments include providing a gate stack, with source/drain regions at opposite sides thereof, and an STI layer on a silicon substrate; forming a TSV trench, laterally separated from the gate stack, through the STI layer and the silicon substrate; forming an isolation layer on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; forming a TSV in the TSV trench; forming a dielectric cap over the isolation layer and the TSV; and forming a source/drain contact through the dielectric cap and the isolation layer down to the source/drain contract regions.

公开(公告)号：US09570403B2

公开(公告)日：2017-02-14

申请号：US15179593

申请日：2016-06-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Qing Cao ,  Kangguo Cheng ,  Fei Liu

IPC分类号： H01L21/00 ,  H01L23/544 ,  H01L29/06 ,  H01L29/78 ,  H01L29/861 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L23/00 ,  H01L29/32 ,  H01L29/66 ,  H01L29/772 ,  H04L9/32

CPC分类号： H01L23/544 ,  G09C1/00 ,  H01L21/0243 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02521 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02667 ,  H01L21/3083 ,  H01L21/31144 ,  H01L23/576 ,  H01L29/0692 ,  H01L29/32 ,  H01L29/6609 ,  H01L29/66409 ,  H01L29/66969 ,  H01L29/772 ,  H01L29/78 ,  H01L29/861 ,  H01L29/868 ,  H01L2223/5444 ,  H04L9/3278

摘要： A first trench having a first aspect ratio and a second trench having a second aspect ratio that is greater than the first trench are provided into a material stack of a semiconductor substrate and a dielectric material. An epitaxial semiconductor material having a different lattice constant than the substrate is then grown within each of the first and second trenches. The semiconductor material which is epitaxially formed in the first trench has an upper semiconductor material portion that is entirely defect free, while the semiconductor material which is epitaxially formed in the second trench has defects that randomly propagate to the topmost surface of the semiconductor material. At least one semiconductor device is then formed on each epitaxially grown semiconductor material. The at least one semiconductor device located on the epitaxially grown semiconductor material formed in the second trench is a physical unclonable function device.

摘要翻译： 具有第一纵横比的第一沟槽和具有大于第一沟槽的第二纵横比的第二沟槽被提供到半导体衬底和电介质材料的材料堆叠中。 然后在每个第一和第二沟槽内生长具有与衬底不同的晶格常数的外延半导体材料。 在第一沟槽中外延形成的半导体材料具有完全无缺陷的上半导体材料部分，而在第二沟槽中外延形成的半导体材料具有随机地传播到半导体材料的最上表面的缺陷。 然后在每个外延生长的半导体材料上形成至少一个半导体器件。 位于第二沟槽中形成的外延生长的半导体材料上的至少一个半导体器件是物理不可克隆功能器件。

公开(公告)号：US20160358906A1

公开(公告)日：2016-12-08

申请号：US15242684

申请日：2016-08-22

申请人： MagnaChip Semiconductor, Ltd.

发明人： Francois HEBERT

IPC分类号： H01L27/06 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78 ,  H01L27/07 ,  H01L29/872 ,  H01L29/10

CPC分类号： H01L27/0629 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/772 ,  H01L29/7827 ,  H01L29/872

摘要： A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.

摘要翻译： 提供具有嵌入肖特基二极管的半导体器件及其制造方法。 具有肖特基二极管的半导体器件包括：第一导电类型的外延层，第二导电类型的主体层和按顺序布置的第一导电类型的源极层; 从源极层延伸到外延层的一部分的栅极沟槽; 形成与所述栅沟槽预定距离并从所述源层延伸到所述外延层的一部分的主体沟槽; 以及第二导电类型的保护环，其与主体沟槽的外壁接触并形成在外延层中。

公开(公告)号：US20160293774A1

公开(公告)日：2016-10-06

申请号：US15178391

申请日：2016-06-09

申请人： Intel Corporation

发明人： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Robert S. Chau

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/205 ,  H01L29/423 ,  H01L29/04 ,  H01L29/20

CPC分类号： H01L29/78696 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/02538 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66409 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78681

摘要： A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

公开(公告)号：US09441298B2

公开(公告)日：2016-09-13

申请号：US14939202

申请日：2015-11-12

申请人： Applied Materials, Inc.

发明人： Khaled Z. Ahmed ,  Prabu Gopalraja ,  Atif Noori ,  Mei Chang

IPC分类号： H01L21/44 ,  C23C16/52 ,  H01L21/768 ,  H01L21/67 ,  H01L23/482 ,  H01L29/772 ,  H01L21/285 ,  C23C14/22 ,  C23C16/02 ,  C23C16/455

CPC分类号： C23C16/52 ,  C23C14/22 ,  C23C16/0227 ,  C23C16/45544 ,  H01L21/28525 ,  H01L21/6715 ,  H01L21/6719 ,  H01L21/67207 ,  H01L21/76843 ,  H01L23/4827 ,  H01L29/772 ,  H01L2924/0002 ,  H01L2924/00

摘要： Described are apparatus and methods for forming films comprise indium and arsenic. In particular, these films may be formed in a configuration of two or more chambers under “load lock” conditions. These films may include additional components as dopants, such as aluminum and/or gallium. Such films can be used in metal/silicon contacts having low contact resistances. Also disclosed are devices including the films comprising indium arsenide.