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公开(公告)号:US09048103B2
公开(公告)日:2015-06-02
申请号:US11988305
申请日:2006-06-26
申请人: Yoshio Shimoida , Hideaki Tanaka , Tetsuya Hayashi , Masakatsu Hoshi , Shigeharu Yamagami , Noriaki Kawamoto , Takayuki Kitou , Mineo Miura , Takashi Nakamura
发明人: Yoshio Shimoida , Hideaki Tanaka , Tetsuya Hayashi , Masakatsu Hoshi , Shigeharu Yamagami , Noriaki Kawamoto , Takayuki Kitou , Mineo Miura , Takashi Nakamura
IPC分类号: H01L21/336 , H01L21/3105 , H01L29/78 , H01L21/04 , H01L29/267 , H01L29/66 , H01L29/16 , H01L29/772
CPC分类号: H01L21/049 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要: A method for producing a semiconductor device (20) is disclosed. The semiconductor device (20) includes: 1) a semiconductor substrate (1, 2), 2) a hetero semiconductor area (3) configured to contact a first main face (1A) of the semiconductor substrate (1, 2) and different from the semiconductor substrate (1, 2) in band gap, 3) a gate electrode (7) contacting, via a gate insulating film (6), a part of a junction part (13) between the hetero semiconductor area (3) and the semiconductor substrate (1, 2), 4) a source electrode (8) configured to connect to the hetero semiconductor area (3), and 5) a drain electrode (9) configured to make an ohmic connection with the semiconductor substrate (1, 2). The method includes the following sequential operations: i) forming the gate insulating film (6); and ii) nitriding the gate insulating film (6).
摘要翻译: 公开了一种用于制造半导体器件(20)的方法。 半导体器件(20)包括:1)半导体衬底(1,2),2)异质半导体区域(3),被配置为接触半导体衬底(1,2)的第一主面(1A) 所述半导体衬底(1,2)具有带隙,3)栅极电极(7)经由栅极绝缘膜(6)与所述异质半导体区域(3)之间的接合部分(13)的一部分 半导体衬底(1,2),4)构造成连接到所述异质半导体区域(3)的源电极(8),以及5)被配置为与所述半导体衬底(1,2)形成欧姆连接的漏电极(9) 2)。 该方法包括以下顺序操作:i)形成栅绝缘膜(6); 和ii)氮化所述栅极绝缘膜(6)。
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公开(公告)号:US08546814B2
公开(公告)日:2013-10-01
申请号:US13258452
申请日:2010-03-23
申请人: Yuki Nakano , Shuhei Mitani , Mineo Miura
发明人: Yuki Nakano , Shuhei Mitani , Mineo Miura
IPC分类号: H01L31/0312
CPC分类号: H01L29/7816 , H01L29/045 , H01L29/1045 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/45 , H01L29/66068 , H01L29/7811 , H01L29/7813
摘要: A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type, each formed in a region extending from the surface of the semiconductor layer to a halfway portion of the same in the thickness direction, and each spaced apart from each other in a direction perpendicular to the thickness direction; source regions of the first conductivity type, each formed on the surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film. In the semiconductor layer, trenches extending between two neighboring source regions are formed by digging from the source of the semiconductor layer, the inside surface of the trenches are covered by the gate insulating film, and the gate electrodes comprise surface-facing parts, which face the surface of the semiconductor layer, and buried parts, which are buried in the trenches.
摘要翻译: 一种半导体器件,包括第一导电类型的半导体层; 多个第二导电类型的主体区域,各自形成在从半导体层的表面延伸到其厚度方向的中间部分的区域中,并且在垂直于厚度的方向上彼此间隔开 方向; 源区域,每个源区域形成在每个体区域的表面层部分上并与每个身体区域的边缘隔开; 形成在所述半导体层上的栅极绝缘膜; 以及形成在栅极绝缘膜上的栅电极。 在半导体层中,通过从半导体层的源进行挖掘来形成在两个相邻的源极区之间延伸的沟槽,沟槽的内表面被栅极绝缘膜覆盖,并且栅电极包括面向表面的部分 半导体层的表面和埋在沟槽中的埋藏部分。
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3.
公开(公告)号:US08222648B2
公开(公告)日:2012-07-17
申请号:US11991249
申请日:2006-08-22
IPC分类号: H01L29/24
CPC分类号: H01L29/66068 , H01L21/049 , H01L21/31666 , H01L29/1608 , H01L29/513 , H01L29/518 , H01L29/7395 , H01L29/7802
摘要: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).
摘要翻译: 碳化硅半导体器件(90)包括:1)碳化硅衬底(1); 2)由多晶硅制成的栅电极(7) 和3)夹在所述碳化硅衬底(1)和所述栅电极(7)之间的ONO绝缘膜(9),从而形成栅极结构,所述ONO绝缘膜(9)包括从所述碳化硅衬底 (1):a)第一氧化硅膜(O)(10),b)SiN膜(N)(11),和c)SiN热氧化膜(O)(12,12a,12b)。 氮在以下位置中的至少一个中包括:i)在第一氧化物硅膜(O)(10)中和在碳化硅衬底(1)附近,以及ii)在碳化硅衬底 (1)和第一氧化硅膜(O)(10)。
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公开(公告)号:US20090026497A1
公开(公告)日:2009-01-29
申请号:US11988305
申请日:2006-06-26
申请人: Yoshio Shimoida , Hideaki Tanaka , Tetsuya Hayashi , Masakatsu Hoshi , Shigeharu Yamagami , Noriaki Kawamoto , Takayuki Kitou , Mineo Miura , Takashi Nakamura
发明人: Yoshio Shimoida , Hideaki Tanaka , Tetsuya Hayashi , Masakatsu Hoshi , Shigeharu Yamagami , Noriaki Kawamoto , Takayuki Kitou , Mineo Miura , Takashi Nakamura
IPC分类号: H01L21/336 , H01L29/78
CPC分类号: H01L21/049 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要: A method for producing a semiconductor device (20) is disclosed. The semiconductor device (20) includes: 1) a semiconductor substrate (1, 2), 2) a hetero semiconductor area (3) configured to contact a first main face (1A) of the semiconductor substrate (1, 2) and different from the semiconductor substrate (1, 2) in band gap, 3) a gate electrode (7) contacting, via a gate insulating film (6), a part of a junction part (13) between the hetero semiconductor area (3) and the semiconductor substrate (1, 2), 4) a source electrode (8) configured to connect to the hetero semiconductor area (3), and 5) a drain electrode (9) configured to make an ohmic connection with the semiconductor substrate (1, 2). The method includes the following sequential operations: i) forming the gate insulating film (6); and ii) nitriding the gate insulating film (6).
摘要翻译: 公开了一种用于制造半导体器件(20)的方法。 半导体器件(20)包括:1)半导体衬底(1,2),2)异质半导体区域(3),被配置为接触半导体衬底(1,2)的第一主面(1A) 所述半导体衬底(1,2)具有带隙,3)栅极电极(7)经由栅极绝缘膜(6)与所述异质半导体区域(3)之间的接合部分(13)的一部分 半导体衬底(1,2),4)构造成连接到所述异质半导体区域(3)的源电极(8),以及5)被配置为与所述半导体衬底(1,2)形成欧姆连接的漏电极(9) 2)。 该方法包括以下顺序操作:i)形成栅极绝缘膜(6); 和ii)氮化所述栅极绝缘膜(6)。
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公开(公告)号:US09136378B2
公开(公告)日:2015-09-15
申请号:US13824380
申请日:2011-09-15
申请人: Keiji Okumura , Mineo Miura , Katsuhisa Nagao , Shuhei Mitani
发明人: Keiji Okumura , Mineo Miura , Katsuhisa Nagao , Shuhei Mitani
IPC分类号: H01L29/66 , H01L29/78 , H01L29/423 , H01L21/04 , H01L29/04 , H01L29/06 , H01L29/16 , H01L29/45 , H01L29/51
CPC分类号: H01L29/7827 , H01L21/046 , H01L21/049 , H01L29/045 , H01L29/0619 , H01L29/0696 , H01L29/1608 , H01L29/42368 , H01L29/45 , H01L29/518 , H01L29/66068 , H01L29/66666 , H01L29/7802 , H01L29/7811
摘要: A semiconductor device includes a first conductive-type semiconductor layer, a second conductive-type body region formed in a surficial portion of the semiconductor layer, a first conductive-type source region formed in a surficial portion of the body region, a gate insulating film provided on the semiconductor layer and containing nitrogen atoms, the gate insulating film including a first portion in contact with the semiconductor layer outside the body region, a second portion in contact with the body region, and a third portion in contact with the source region, and a gate electrode provided on the gate insulating film in an area extending across the semiconductor layer outside the body region, the body region, and the source region. The third portion of the gate insulating film has a thickness greater than the thickness of the first portion and the thickness of the second portion.
摘要翻译: 半导体器件包括第一导电类型半导体层,形成在半导体层的表面部分中的第二导电型体区域,形成在体区的表面部分中的第一导电型源极区域,栅极绝缘膜 设置在所述半导体层上并且含有氮原子的栅极绝缘膜,所述栅极绝缘膜包括与所述体区域外部的所述半导体层接触的第一部分,与所述主体区域接触的第二部分和与所述源极区域接触的第三部分, 以及栅极电极,设置在栅极绝缘膜上的延伸穿过体区,身体区域和源区域之外的半导体层的区域中。 栅极绝缘膜的第三部分的厚度大于第一部分的厚度和第二部分的厚度。
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公开(公告)号:US07510986B2
公开(公告)日:2009-03-31
申请号:US10585108
申请日:2004-12-21
申请人: Mineo Miura
发明人: Mineo Miura
IPC分类号: H01L21/00
CPC分类号: H01L29/1608 , H01L21/0445 , H01L21/324 , H01L21/67103
摘要: In a production process for a semiconductor device employing an SiC semiconductor substrate (1), the SiC semiconductor substrate (1) is mounted on a susceptor (23), and a C heating member (3) of carbon is placed on a surface of the SiC semiconductor substrate (1). An annealing process is performed to form an impurity region in the surface of the SiC semiconductor substrate (1) by causing the susceptor (23) and the C heating member (3) to generate heat at high temperatures.
摘要翻译: 在使用SiC半导体基板(1)的半导体装置的制造方法中,将SiC半导体基板(1)安装在基座(23)上,将碳加热构件(3)放置在 SiC半导体衬底(1)。 通过使基座(23)和C加热部件(3)在高温下发热,进行退火处理,以在SiC半导体基板(1)的表面形成杂质区域。
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7.
公开(公告)号:US20090050898A1
公开(公告)日:2009-02-26
申请号:US11991249
申请日:2006-08-22
IPC分类号: H01L29/24 , H01L21/316
CPC分类号: H01L29/66068 , H01L21/049 , H01L21/31666 , H01L29/1608 , H01L29/513 , H01L29/518 , H01L29/7395 , H01L29/7802
摘要: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).
摘要翻译: 碳化硅半导体器件(90)包括:1)碳化硅衬底(1); 2)由多晶硅制成的栅电极(7) 和3)夹在所述碳化硅衬底(1)和所述栅电极(7)之间的ONO绝缘膜(9),从而形成栅极结构,所述ONO绝缘膜(9)包括从所述碳化硅衬底 (1):a)第一氧化硅膜(O)(10),b)SiN膜(N)(11),和c)SiN热氧化膜(O)(12,12a,12b)。 氮在以下位置中的至少一个中包括:i)在第一氧化物硅膜(O)(10)中和在碳化硅衬底(1)附近,以及ii)在碳化硅衬底 (1)和第一氧化硅膜(O)(10)。
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公开(公告)号:US20130248981A1
公开(公告)日:2013-09-26
申请号:US13824380
申请日:2011-09-15
申请人: Keiji Okumura , Mineo Miura , Katsuhisa Nagao , Shuhei Mitani
发明人: Keiji Okumura , Mineo Miura , Katsuhisa Nagao , Shuhei Mitani
CPC分类号: H01L29/7827 , H01L21/046 , H01L21/049 , H01L29/045 , H01L29/0619 , H01L29/0696 , H01L29/1608 , H01L29/42368 , H01L29/45 , H01L29/518 , H01L29/66068 , H01L29/66666 , H01L29/7802 , H01L29/7811
摘要: A semiconductor device includes a first conductive-type semiconductor layer, a second conductive-type body region formed in a surficial portion of the semiconductor layer, a first conductive-type source region formed in a surficial portion of the body region, a gate insulating film provided on the semiconductor layer and containing nitrogen atoms, the gate insulating film including a first portion in contact with the semiconductor layer outside the body region, a second portion in contact with the body region, and a third portion in contact with the source region, and a gate electrode provided on the gate insulating film in an area extending across the semiconductor layer outside the body region, the body region, and the source region. The third portion of the gate insulating film has a thickness greater than the thickness of the first portion and the thickness of the second portion.
摘要翻译: 半导体器件包括第一导电类型半导体层,形成在半导体层的表面部分中的第二导电型体区域,形成在体区的表面部分中的第一导电型源极区域,栅极绝缘膜 设置在所述半导体层上并且含有氮原子的栅极绝缘膜,所述栅极绝缘膜包括与所述体区域外部的所述半导体层接触的第一部分,与所述主体区域接触的第二部分和与所述源极区域接触的第三部分, 以及栅极电极,设置在栅极绝缘膜上的延伸穿过体区,身体区域和源区域之外的半导体层的区域中。 栅极绝缘膜的第三部分的厚度大于第一部分的厚度和第二部分的厚度。
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公开(公告)号:US20130009256A1
公开(公告)日:2013-01-10
申请号:US13635312
申请日:2011-03-30
申请人: Keiji Okumura , Mineo Miura , Yuki Nakano , Noriaki Kawamoto
发明人: Keiji Okumura , Mineo Miura , Yuki Nakano , Noriaki Kawamoto
IPC分类号: H01L29/78
CPC分类号: H01L29/66734 , H01L21/02164 , H01L21/02271 , H01L21/02529 , H01L21/0254 , H01L21/0465 , H01L21/31111 , H01L29/0615 , H01L29/0619 , H01L29/0657 , H01L29/0696 , H01L29/0886 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/45 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66068 , H01L29/7811 , H01L29/7813
摘要: The semiconductor device according to the present invention includes a semiconductor layer of a first conductivity type, body regions of a second conductivity type plurally formed on a surface layer portion of the semiconductor layer at an interval, a source region of the first conductivity type formed on a surface layer portion of each body region, a gate insulating film provided on the semiconductor layer to extend between the body regions adjacent to each other, a gate electrode provided on the gate insulating film and opposed to the body regions, and a field relaxation portion provided between the body regions adjacent to each other for relaxing an electric field generated in the gate insulating film.
摘要翻译: 根据本发明的半导体器件包括第一导电类型的半导体层,第二导电类型的主体区域,多个以一定间隔形成在半导体层的表面层部分上,第一导电类型的源极区形成在 每个体区的表层部分,设置在半导体层上以在彼此相邻的主体区域之间延伸的栅极绝缘膜,设置在栅极绝缘膜上并与身体区域相对的栅电极,以及场弛豫部分 设置在彼此相邻的主体区域之间,用于放松在栅极绝缘膜中产生的电场。
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10.
公开(公告)号:US20120064731A1
公开(公告)日:2012-03-15
申请号:US13299136
申请日:2011-11-17
IPC分类号: H01L21/316
CPC分类号: H01L29/66068 , H01L21/049 , H01L21/31666 , H01L29/1608 , H01L29/513 , H01L29/518 , H01L29/7395 , H01L29/7802
摘要: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).
摘要翻译: 一种碳化硅半导体器件(90),包括:1)碳化硅衬底(1); 2)由多晶硅制成的栅电极(7) 和3)夹在所述碳化硅衬底(1)和所述栅电极(7)之间的ONO绝缘膜(9),从而形成栅极结构,所述ONO绝缘膜(9)包括从所述碳化硅衬底 (1):a)第一氧化硅膜(O)(10),b)SiN膜(N)(11),和c)SiN热氧化膜(O)(12,12a,12b)。 氮在以下位置中的至少一个中包括:i)在第一氧化物硅膜(O)(10)中和在碳化硅衬底(1)附近,以及ii)在碳化硅衬底 (1)和第一氧化硅膜(O)(10)。
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