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52 条记录 (耗时 0.017 秒)

    Data processing apparatus
    1.
    发明授权
    Data processing apparatus 有权
    数据处理装置

    公开(公告)号：US08918646B2

    公开(公告)日：2014-12-23

    申请号：US13456630

    申请日：2012-04-26

    申请人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

    发明人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

    IPC分类号： H04L29/06 ,  G06F21/72 ,  H04L9/06

    CPC分类号： G06F21/72 ,  H04L9/0643 ,  H04L63/0485 ,  H04L63/123 ,  H04L63/166 ,  H04L2209/125

    摘要： In the configuration performing a data processing by a hardware processing circuit (accelerator), to provide a technology capable of improving a poorness of processing efficiency by multiple accesses to the data, the following solving means are provided. A network data processing accelerator of the present network data processing apparatus comprises processing units corresponding to each processing of an encryption/decryption, a message authentication, and a checksum, and in the data processing including a combination of each processing, accesses for the same data of the memory and the like through a bus I/F unit and the like is collected together into one time, and a pipeline processing is performed using the least common multiple of the data processing unit of each processing.

    摘要翻译： 在通过硬件处理电路（加速器）执行数据处理的配置中，为了提供能够通过多次访问数据来改善处理效率差的技术，提供了以下解决方案。 本网络数据处理装置的网络数据处理加速器包括对应于加密/解密，消息认证和校验和的每个处理的处理单元，并且在包括每个处理的组合的数据处理中，对相同数据的访问 通过总线I / F单元等将存储器等等一起收集在一起，并且使用每个处理的数据处理单元的最小公倍数来执行流水线处理。

    DMA CONTROLLER
    3.
    发明申请
    DMA CONTROLLER 失效
    DMA控制器

    公开(公告)号：US20100257288A1

    公开(公告)日：2010-10-07

    申请号：US12595381

    申请日：2008-03-21

    申请人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

    发明人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28 ,  Y02D10/14

    摘要： A DMA controller achieving real-time control of a DMA transfer relating to periodically operated peripheral devices at a low cost and with low power consumption. A typical embodiment of the invention is a DMA controller having: a counter for counting time; a counter comparator comparing a value of the counter and a counter value indicating an expected time of a DMA transfer; a peripheral device read unit reading a register of the peripheral device to acquire a state of a peripheral device by; and a state comparator comparing a value of the register read by the peripheral device read unit and a start condition of the DMA transfer, in which, with being triggered by establishment of a comparison result by the counter comparator, in accordance with a specified order, a processing of updating the counter value indicating the expected time of a DMA transfer to a value indicating a next expected time, a read of the register of the peripheral device by the peripheral device read unit, a comparison by the state comparator, and a DMA transfer on the condition that the comparison result by the state comparator is established are executed.

    摘要翻译： DMA控制器以低成本和低功耗实现与周期性操作的外围设备相关的DMA传输的实时控制。 本发明的典型实施例是一种DMA控制器，具有：计数时间的计数器; 比较计数器的值和表示DMA传送的预期时间的计数器值的计数器比较器; 外围设备读取单元，读取外围设备的寄存器，以通过以下方式获取外围设备的状态; 以及状态比较器，比较由外围设备读取单元读取的寄存器的值和DMA传输的开始条件，其中，通过由计数器比较器建立比较结果而触发，根据指定的顺序， 将指示DMA传输的预期时间的计数器值更新为指示下一个预期时间的值的处理，外围设备读取单元对外围设备的寄存器的读取，状态比较器的比较以及DMA 在状态比较器的比较结果建立的条件下进行转移。

    Method of Recording/Reproducing Digital Data and Apparatus for Same
    4.
    发明申请
    Method of Recording/Reproducing Digital Data and Apparatus for Same 有权
    记录/再现数字数据的方法及其设备

    公开(公告)号：US20080294947A1

    公开(公告)日：2008-11-27

    申请号：US12180450

    申请日：2008-07-25

    申请人： Taku HOSHIZAWA ,  Shigeki TAIRA ,  Osamu KAWAMAE

    发明人： Taku HOSHIZAWA ,  Shigeki TAIRA ,  Osamu KAWAMAE

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/2732 ,  G11B20/18 ,  G11B20/1803 ,  G11B20/1866 ,  H03M13/03 ,  H03M13/271 ,  H03M13/29

    摘要： A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

    摘要翻译： 数字数据记录/再现方法包括以下步骤：对208行ECC块的每个PI代码的PI代码交织数据; 并通过在PI代码上分散错误将短突发错误转换为随机错误。 此外，数字数据记录/再现方法通过使用尽可能不同的交错规则，通过对各个PI代码执行该处理，从而增加了随机产生的几个字节到几十个字节的纠错能力，而不改变突发错误校正长度 另一个。

    DMA controller
    6.
    发明授权
    DMA controller 失效
    DMA控制器

    公开(公告)号：US08266340B2

    公开(公告)日：2012-09-11

    申请号：US13437297

    申请日：2012-04-02

    申请人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

    发明人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

    IPC分类号： G06F13/28 ,  G06F13/00

    CPC分类号： G06F13/28 ,  Y02D10/14

    摘要： The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.

    摘要翻译： DMA控制器包括外围设备读取单元，用于读取外围设备的状态，状态比较器，传送单元，寄存器和外围设备写入单元，以根据DMA中的内容在外围设备中写入数据 执行转移，中断选择单元选择多个中断信号之一来确定外围设备读取单元，状态比较器和传送单元是否处于执行操作的定时。 基于这些操作，状态比较器确定是否启动DMA传输，并且传送单元执行外围设备之间的数据传输。

    Recording method for recording data on a recording medium
    10.
    发明授权
    Recording method for recording data on a recording medium 有权
    用于在记录介质上记录数据的记录方法

    公开(公告)号：US07620874B2

    公开(公告)日：2009-11-17

    申请号：US11822466

    申请日：2007-07-06

    申请人： Osamu Kawamae ,  Taku Hoshizawa ,  Harukazu Miyamoto ,  Shigeki Taira ,  Yukari Katayama

    发明人： Osamu Kawamae ,  Taku Hoshizawa ,  Harukazu Miyamoto ,  Shigeki Taira ,  Yukari Katayama

    IPC分类号： H03M13/00

    CPC分类号： G11B20/00768 ,  G11B20/1217 ,  G11B20/1833 ,  G11B20/1866 ,  G11B27/105 ,  G11B27/329 ,  G11B2020/1222 ,  G11B2020/1265 ,  G11B2020/1292 ,  G11B2020/1294 ,  G11B2020/1836 ,  G11B2220/218 ,  G11B2220/2562

    摘要： If a large minimum data unit for recorded data is used to record a small data amount of management information, the recording time is long, and furthermore when a WO (write once) is used as the recording medium, the number of recording operations which can be performed is restricted. To solve the above problems, the present invention can record data in a management area in units smaller than ordinary units for recorded data to suitably record information in a limited management area and thereby efficiently use the user data area. At that time, the present invention simplifies interleave processing usually applied to ordinary recorded data, and performs the simplified interleave processing on a data structure (for data of small size) of the present invention so as to ensure the signal processing compatibility between the ordinary data and data having the data structure according to the present invention.

    摘要翻译： 如果用于记录数据的大的最小数据单元用于记录管理信息的小数据量，则记录时间长，此外当使用WO（一次写入）作为记录介质时，可以记录操作的数量 被执行是受限制的。 为了解决上述问题，本发明可以以小于普通单位的单位在管理区域中记录数据以在有限的管理区域中适当地记录信息，从而有效地使用用户数据区域。 此时，本发明简化了通常适用于普通记录数据的交错处理，并且对本发明的数据结构（小尺寸数据）执行简化的交错处理，以确保普通数据之间的信号处理兼容性 以及具有根据本发明的数据结构的数据。