公开(公告)号：US5760606A

公开(公告)日：1998-06-02

申请号：US633683

申请日：1996-04-17

申请人： Hiroshige Hirano ,  Shigeo Chaya ,  Toshiyuki Honda

发明人： Hiroshige Hirano ,  Shigeo Chaya ,  Toshiyuki Honda

IPC分类号： H03K3/356 ,  H03K17/0416 ,  H03K17/10 ,  H03K19/0185

CPC分类号： H03K3/356147 ,  H03K17/04163 ,  H03K17/102 ,  H03K3/356052

摘要： A switch circuit having a high withstanding voltage and low driving ability and another switch circuit having a low withstanding voltage and high driving ability are connected to a specified node in parallel. When discharging the charges of the specified node, the switch circuit having the high withstanding voltage is turned ON and the switch circuit having the great driving ability is then turned ON. Accordingly, it is sufficient that only the transition of the logical voltage of a switch circuit having the high withstanding voltage is taken into consideration to set the ON timing of a switch circuit having the high driving ability. Consequently, timing setting can be performed easily. After the switch circuit having the high driving ability is turned ON, a discharge path for the charges of the specified node takes two paths which passes through both switch circuits in parallel. Consequently, an operating speed can be increased.

摘要翻译： 具有高耐受电压和低驱动能力的开关电路以及具有低耐压和高驱动能力的另一开关电路并联连接到指定节点。 当放电指定节点的电荷时，具有高耐受电压的开关电路导通，并且具有较大驱动能力的开关电路然后导通。 因此，仅考虑具有高耐受电压的开关电路的逻辑电压的转变，以设定具有高驱动能力的开关电路的导通定时就足够了。 因此，可以容易地进行定时设定。 在具有高驱动能力的开关电路被接通之后，用于指定节点的电荷的放电路径需要并行通过两个开关电路的两条路径。 因此，可以提高运转速度。

公开(公告)号：US20120001177A1

公开(公告)日：2012-01-05

申请号：US13232516

申请日：2011-09-14

申请人： Asako Miyoshi ,  Shigeo Chaya

发明人： Asako Miyoshi ,  Shigeo Chaya

IPC分类号： H01L23/538 ,  H01L23/535

CPC分类号： H01L25/0657 ,  H01L23/3107 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2225/06568

摘要： In a multi-chip semiconductor device, a second semiconductor chip is stacked on a first semiconductor chip with an adhesive layer being interposed therebetween, and the first and second semiconductor chips are sealed by resin containing a mixture of, e.g., a filler. The first semiconductor chip includes a first region on a surface of which the second semiconductor chip is stacked, and a second region on a surface of which the second semiconductor chip does not stacked. In one of interconnect layers including an uppermost layer, a wiring pattern is not provided, which extends across a border between the first and second regions.

摘要翻译： 在多芯片半导体器件中，第二半导体芯片堆叠在第一半导体芯片上，其间夹有粘合剂层，并且第一和第二半导体芯片被包含例如填料的混合物的树脂密封。 第一半导体芯片包括其第二半导体芯片堆叠的表面上的第一区域和第二半导体芯片不堆叠的表面上的第二区域。 在包括最上层的互连层之一中，不设置延伸穿过第一和第二区域之间的边界的布线图案。

公开(公告)号：US06667907B2

公开(公告)日：2003-12-23

申请号：US10395193

申请日：2003-03-25

申请人： Shigeo Chaya ,  Masanori Matsuura

发明人： Shigeo Chaya ,  Masanori Matsuura

IPC分类号： G11C1134

CPC分类号： G11C16/32 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14

摘要： The semiconductor memory of this invention includes a memory cell, a control word line selector/deriver circuit, a well driver circuit, a source line selector/deriver circuit, a pulse generation circuit for outputting a pulse signal in injecting electrons into a floating gate of the memory cell, a first delay circuit, a second delay circuit and a third delay circuit. The control word line selector/deriver circuit changes the potential of a control word line in response to a first delay signal received from the first delay circuit, the well driver circuit changes the potential of a well in response to a second delay signal received from the second delay circuit, and the source line selector/deriver circuit changes the potential of a source line in response to a third delay signal received from the third delay circuit.

摘要翻译： 本发明的半导体存储器包括存储单元，控制字线选择器/引导电路，阱驱动器电路，源极线选择器/引导电路，用于在将电子注入到浮动栅极的浮动栅极中输出脉冲信号的脉冲发生电路 存储单元，第一延迟电路，第二延迟电路和第三延迟电路。 响应于从第一延迟电路接收到的第一延迟信号，控制字线选择器/引导电路改变控制字线的电位，阱驱动器电路响应于从第二延迟信号接收的第二延迟信号改变阱的电位 第二延迟电路，并且源极线选择器/导流电路响应于从第三延迟电路接收的第三延迟信号改变源极线的电位。