公开(公告)号：US06667907B2

公开(公告)日：2003-12-23

申请号：US10395193

申请日：2003-03-25

申请人： Shigeo Chaya ,  Masanori Matsuura

发明人： Shigeo Chaya ,  Masanori Matsuura

IPC分类号： G11C1134

CPC分类号： G11C16/32 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14

摘要： The semiconductor memory of this invention includes a memory cell, a control word line selector/deriver circuit, a well driver circuit, a source line selector/deriver circuit, a pulse generation circuit for outputting a pulse signal in injecting electrons into a floating gate of the memory cell, a first delay circuit, a second delay circuit and a third delay circuit. The control word line selector/deriver circuit changes the potential of a control word line in response to a first delay signal received from the first delay circuit, the well driver circuit changes the potential of a well in response to a second delay signal received from the second delay circuit, and the source line selector/deriver circuit changes the potential of a source line in response to a third delay signal received from the third delay circuit.

摘要翻译： 本发明的半导体存储器包括存储单元，控制字线选择器/引导电路，阱驱动器电路，源极线选择器/引导电路，用于在将电子注入到浮动栅极的浮动栅极中输出脉冲信号的脉冲发生电路 存储单元，第一延迟电路，第二延迟电路和第三延迟电路。 响应于从第一延迟电路接收到的第一延迟信号，控制字线选择器/引导电路改变控制字线的电位，阱驱动器电路响应于从第二延迟信号接收的第二延迟信号改变阱的电位 第二延迟电路，并且源极线选择器/导流电路响应于从第三延迟电路接收的第三延迟信号改变源极线的电位。

公开(公告)号：US07835169B2

公开(公告)日：2010-11-16

申请号：US12368622

申请日：2009-02-10

申请人： Yasuo Murakuki ,  Yasushi Gohou ,  Shunichi Iwanari ,  Masanori Matsuura ,  Yoshiaki Nakao

发明人： Yasuo Murakuki ,  Yasushi Gohou ,  Shunichi Iwanari ,  Masanori Matsuura ,  Yoshiaki Nakao

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of the memory cells and each of the cell plate lines being connected to the memory cells of a corresponding one of the rows. Each of the memory cell arrays includes a plurality of word lines each of which corresponds to each of the rows of the memory cells in the memory cell array. The number of the memory cells connected to each of the cell plate lines is larger than the number of the memory cells connected to one of the word lines corresponding to the each of the cell plate lines.

摘要翻译： 半导体存储器件包括多个存储单元阵列，每个存储单元阵列包括以矩阵图案排列的多个存储单元，以及多个存储单元阵列共享的单元板板线，每个单元板线对应于 存储单元的行和每个单元格板线连接到相应行之一的存储单元。 每个存储单元阵列包括多个字线，每个字线对应于存储单元阵列中存​​储单元的行中的每一行。 连接到每个单元格板行的存储单元的数量大于连接到与每个单元格板行相对应的一个字线的存储单元的数量。

公开(公告)号：US20080313391A1

公开(公告)日：2008-12-18

申请号：US12136340

申请日：2008-06-10

申请人： Shunichi Iwanari ,  Hisakazu Kotani ,  Masanori Matsuura

发明人： Shunichi Iwanari ,  Hisakazu Kotani ,  Masanori Matsuura

IPC分类号： G06F12/02

CPC分类号： G11C16/26 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1063

摘要： A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region.

摘要翻译： 一种半导体存储器件，包括：包括布置在其中的多个存储单元的单元阵列块; 以及控制器，其中所述控制器控制所述半导体存储器件，使得：在完成从所述单元阵列中的第一区域读出的数据的输出的操作完成之前，开始从所述单元阵列块中的第二区域读出数据的操作 块; 在从第一区域读出的数据的输出操作完成之后连续地输出从第二区域读出的数据。

公开(公告)号：US20080028132A1

公开(公告)日：2008-01-31

申请号：US11798679

申请日：2007-05-16

申请人： Masanori Matsuura ,  Yasushi Gohou ,  Shunichi Iwanari ,  Yoshiaki Nakao ,  Hisakazu Kotani ,  Junichi Kato ,  Satoshi Mishima ,  Motonobu Nishimura ,  Toshiki Mori

发明人： Masanori Matsuura ,  Yasushi Gohou ,  Shunichi Iwanari ,  Yoshiaki Nakao ,  Hisakazu Kotani ,  Junichi Kato ,  Satoshi Mishima ,  Motonobu Nishimura ,  Toshiki Mori

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F13/1668 ,  G06F2212/7203 ,  G11C16/10

摘要： A non-volatile storage device comprises a non-volatile memory into which data is written per unit area, and a memory controller for controlling writing of data into the non-volatile memory. The memory controller comprises a first storage section for holding data input from the outside of the device, a first control section for writing data which is held by the first storage section and whose amount corresponds to the unit area, into the non-volatile memory in a unit area-by-unit area basis, and writing data which is held by the first storage section and whose amount is less than the unit area, into a second storage section, and a second control section for writing data held by the second storage section into the non-volatile memory.

摘要翻译： 非易失性存储装置包括：每单位区域写入数据的非易失性存储器;以及用于控制将数据写入非易失性存储器的存储器控​​制器。 存储器控制器包括用于保存从设备外部输入的数据的第一存储部分，用于将由第一存储部分保存并且其数量对应于单位区域的数据写入到非易失性存储器中的第一控制部分 以单位面积为单位的区域，以及将由第一存储部保持的数量小于单位面积的写入数据写入到第二存储部中，以及第二控制部，用于写入由第二存储器 部分进入非易失性存储器。

公开(公告)号：US06999349B2

公开(公告)日：2006-02-14

申请号：US10781808

申请日：2004-02-20

申请人： Kenji Misumi ,  Atsushi Fujiwara ,  Masanori Matsuura ,  Toshio Nishimoto

发明人： Kenji Misumi ,  Atsushi Fujiwara ,  Masanori Matsuura ,  Toshio Nishimoto

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： A writing operation selecting circuit is provided for selecting a temporary writing operation having a prescribed writing time for a memory cell transistor element and an additional writing operation for the memory cell transistor element. A writing time control circuit is provided for controlling an additional writing operation time by an output signal of the writing operation selecting circuit.

摘要翻译： 提供写入操作选择电路，用于选择对于存储单元晶体管元件具有规定写入时间的暂时写入操作以及用于存储单元晶体管元件的附加写入操作。 提供写入时间控制电路，用于通过写入操作选择电路的输出信号来控制附加写入操作时间。

公开(公告)号：US06898490B2

公开(公告)日：2005-05-24

申请号：US10267537

申请日：2002-10-09

申请人： Tetsuya Yashiki ,  Masanori Matsuura

发明人： Tetsuya Yashiki ,  Masanori Matsuura

IPC分类号： B60R16/02 ,  F02D45/00 ,  G05B15/02 ,  G06F12/00 ,  G06F17/00 ,  G11C16/10 ,  G11C17/00 ,  H04L12/28 ,  G06F19/00

CPC分类号： G11C16/102

摘要： A vehicle controller comprises a first buffer for storing at least one data block, a second buffer for storing at least one data block, and a rewritable non-volatile memory for storing information for controlling a vehicle. The controller receives a data block from an external rewriting device to store it in the first buffer. The data block stored in the first buffer is transferred to the second buffer. The data block stored in the second buffer is written into the memory. When a first data block is written into the memory, a subsequent data block is received. Thus, the time required to rewrite data stored in the nonvolatile memory is reduced.

摘要翻译： 车辆控制器包括用于存储至少一个数据块的第一缓冲器，用于存储至少一个数据块的第二缓冲器和用于存储用于控制车辆的信息的可重写非易失性存储器。 控制器从外部重写装置接收数据块，将其存储在第一缓冲器中。 存储在第一缓冲器中的数据块被传送到第二缓冲器。 存储在第二缓冲器中的数据块被写入存储器。 当第一数据块被写入存储器时，接收后续的数据块。 因此，重写存储在非易失性存储器中的数据所需的时间减少。

公开(公告)号：US06480928B2

公开(公告)日：2002-11-12

申请号：US09802202

申请日：2001-03-08

申请人： Tetsuya Yashiki ,  Masanori Matsuura ,  Naohiko Mizuo

发明人： Tetsuya Yashiki ,  Masanori Matsuura ,  Naohiko Mizuo

IPC分类号： G06F1200

CPC分类号： G11C16/102 ,  G06F8/60

摘要： A memory rewriting system for a vehicle controller is provided. The memory rewriting system transfers a first program from a rewriting device to the vehicle to rewrite a second program stored in a memory of the vehicle controller with the first program. The first program is transferred as data blocks. Each of the data blocks includes a program code field, a first address field and a second address field. The program code field contains a partial program code of the first program. The first address field contains a leading address of the memory in which the partial program code is stored. The second address field contains a leading address of the memory in which a following partial program code transferred by another block is to be stored. The data blocks are assembled in the rewriting device. Each data block is may be a fixed length or a variable length. When the data block is transferred to the vehicle controller, a first address in the first address field of the current transferred data block is compared with a second address in the second address field of the preceding transferred data block. If the first address included in the current data block is not equal to the second address included in the preceding data block, it is determined that the current transferred data block is not correct. The vehicle controller requests the rewriting device to retransfer a correct data block that has said second address in the first address field.

摘要翻译： 提供了一种用于车辆控制器的存储器重写系统。 存储器重写系统将第一程序从重写装置传送到车辆，以用第一程序重写存储在车辆控制器的存储器中的第二程序。 第一个程序作为数据块传送。 每个数据块包括程序代码字段，第一地址字段和第二地址字段。 程序代码字段包含第一程序的部分程序代码。 第一个地址字段包含存储部分程序代码的存储器的前导地址。 第二地址字段包含存储器的前导地址，其中存储由另一个块传送的以下部分程序代码。 数据块被组装在重写装置中。 每个数据块可以是固定长度或可变长度。 当将数据块传送到车辆控制器时，将当前传送数据块的第一地址字段中的第一地址与先前传送数据块的第二地址字段中的第二地址进行比较。 如果当前数据块中包含的第一地址不等于前面数据块中包含的第二地址，则确定当前传送的数据块不正确。 车辆控制器请求重写装置在第一地址字段中重传具有所述第二地址的正确数据块。

公开(公告)号：US07248503B2

公开(公告)日：2007-07-24

申请号：US11242894

申请日：2005-10-05

申请人： Kenji Misumi ,  Atsushi Fujiwara ,  Masanori Matsuura ,  Toshio Nishimoto

发明人： Kenji Misumi ,  Atsushi Fujiwara ,  Masanori Matsuura ,  Toshio Nishimoto

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： A writing operation selecting circuit is provided for selecting a temporary writing operation having a prescribed writing time for a memory cell transistor element and an additional writing operation for the memory cell transistor element. A writing time control circuit is provided for controlling an additional writing operation time by an output signal of the writing operation selecting circuit.

摘要翻译： 提供写入操作选择电路，用于选择对于存储单元晶体管元件具有规定写入时间的暂时写入操作以及用于存储单元晶体管元件的附加写入操作。 提供写入时间控制电路，用于通过写入操作选择电路的输出信号来控制附加写入操作时间。

公开(公告)号：US07171533B2

公开(公告)日：2007-01-30

申请号：US10721097

申请日：2003-11-26

申请人： Masanori Matsuura

发明人： Masanori Matsuura

IPC分类号： G06F12/14

CPC分类号： G06K19/073 ,  G06K19/07363

摘要： A data mask section outputs memory data read from a memory array unit for a predetermined time period that is shifted from an edge timing of a clock signal, while a microcomputer takes in the data output from the data mask section at the edge timing of the clock signal. Thus, the microcomputer is capable of appropriately taking in the memory data only when the frequency of the clock signal is within a predetermined range, and accordingly, it is difficult to fraudulently obtain the memory data. Furthermore, the data mask section may output random data, or the like, during a time period other than the predetermined time period. In such a case, it is difficult to analyze the memory data, and the confidentiality of the memory data is improved.

摘要翻译： 数据屏蔽部分输出从时钟信号的边缘定时偏移了从存储器阵列单元读出的预定时间段的存储器数据，而微计算机在时钟的边沿定时处接收从数据掩码部分输出的数据 信号。 因此，只有当时钟信号的频率在预定范围内时，微计算机能够适当地接收存储器数据，因此难以欺骗地获得存储器数据。 此外，数据掩码部可以在预定时间段之外的时间段期间输出随机数据等。 在这种情况下，难以分析存储器数据，并且提高了存储器数据的机密性。

公开(公告)号：US5621381A

公开(公告)日：1997-04-15

申请号：US464375

申请日：1995-06-05

申请人： Takashi Kawachi ,  Kenji Iwasaki ,  Masanori Matsuura ,  Satoru Ohtsuka ,  Shinichi Kubota ,  Eiji Mutoh

发明人： Takashi Kawachi ,  Kenji Iwasaki ,  Masanori Matsuura ,  Satoru Ohtsuka ,  Shinichi Kubota ,  Eiji Mutoh

IPC分类号： E05B49/00 ,  B60R25/04 ,  B60R25/24 ,  G08B13/00 ,  B60R25/10

CPC分类号： B60R25/04

摘要： A vehicle anti-theft engine control device enables engine control to be continued even if the data in the memory, wherein an ID code checking result has been stored, incurs "bit change" due to noise or the like, causing the data to change into data prohibiting engine control. The control device comprises a plurality of engine start enable flags for storing information on the enable/disable state of the engine control, enable flag registering means for registering "1" (enable) in all flags in response to a start permit signal, re-registering means for registering again, when "1" has been registered in at least one of the flags, "1" (enable) in all other enable flags, and control enabling means for enabling the engine control in accordance with the registered/reregistered enable flag.

摘要翻译： 即使已经存储了ID码检查结果的存储器中的数据由于噪声等而引起“位改变”，车辆防盗引擎控制装置也能够继续发动机控制，导致数据变成 数据禁止引擎控制。 控制装置包括多个用于存储关于发动机控制的启用/禁用状态的信息的发动机启动使能标志，使能标志登记装置用于响应于启动许可信号在所有标志中注册“1”（使能） 登记装置，当在所有其他使能标志中的至少一个标志“1”（使能）中登记了“1”，以及根据注册/重新注册使能的控制使能装置实现引擎控制 旗。