公开(公告)号：US06305095B1

公开(公告)日：2001-10-23

申请号：US09513885

申请日：2000-02-25

Applicant: Kevin T. Look ,  Shih-Cheng Hsueh

Inventor： Kevin T. Look ,  Shih-Cheng Hsueh

IPC: G01B700

CPC classification number: G03F7/70633 ,  G01B7/003 ,  H01L22/34

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

Abstract translation: 描述了掩模对准检测结构，其测量使用电阻元件的集成电路的层之间的未对准的方向和程度，其中电阻随着一维中的未对准而变化。 根据本发明的测量对于工艺变化相对不敏感，并且用于进行这些测量的结构可以与使用标准工艺的集成电路上的其它特征一起形成。 本发明的一个实施例可用于测量两个导电层之间的未对准。 其他实施例测量扩散区域和导体之间以及扩散区域和窗口之间的未对准，通过该窗口将形成其他扩散区域。 根据一个实施例的电路包括行和列解码器，用于独立地选择掩模对准检测结构以减少实现检测结构所需的测试终端的数量。

公开(公告)号：US06436726B1

公开(公告)日：2002-08-20

申请号：US09906286

申请日：2001-07-16

Applicant: Kevin T. Look ,  Shih-Cheng Hsueh

Inventor： Kevin T. Look ,  Shih-Cheng Hsueh

IPC: G01R3126

Abstract: Mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

公开(公告)号：US06393714B1

公开(公告)日：2002-05-28

申请号：US09512779

申请日：2000-02-25

Applicant: Kevin T. Look ,  Shih-Cheng Hsueh

Inventor： Kevin T. Look ,  Shih-Cheng Hsueh

IPC: G01D2100

CPC classification number: G03F7/70633 ,  G03F7/70658 ,  H01L22/34

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

Abstract translation: 描述了掩模对准检测结构，其测量使用电阻元件的集成电路的层之间的未对准的方向和程度，其中电阻随着一维中的未对准而变化。 根据本发明的测量对于工艺变化相对不敏感，并且用于进行这些测量的结构可以与使用标准工艺的集成电路上的其它特征一起形成。 本发明的一个实施例可用于测量两个导电层之间的未对准。 其他实施例测量扩散区域和导体之间以及扩散区域和窗口之间的未对准，通过该窗口将形成其他扩散区域。 根据一个实施例的电路包括行和列解码器，用于独立地选择掩模对准检测结构以减少实现检测结构所需的测试终端的数量。

公开(公告)号：US06878561B2

公开(公告)日：2005-04-12

申请号：US10681549

申请日：2003-10-07

Applicant: Kevin T. Look ,  Shih-Cheng Hsueh

Inventor： Kevin T. Look ,  Shih-Cheng Hsueh

IPC: H01L23/544 ,  H01L21/66

CPC classification number: H01L22/34

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

Abstract translation: 描述了掩模对准检测结构，其测量使用电阻元件的集成电路的层之间的未对准的方向和程度，其中电阻随着一维中的未对准而变化。 根据本发明的测量对于工艺变化相对不敏感，并且用于进行这些测量的结构可以使用标准工艺与集成电路上的其它特征一起形成。 本发明的一个实施例可用于测量两个导电层之间的未对准。 其他实施例测量扩散区域和导体之间以及扩散区域和窗口之间的未对准，通过该窗口将形成其他扩散区域。 根据一个实施例的电路包括行和列解码器，用于独立地选择掩模对准检测结构以减少实现检测结构所需的测试终端的数量。

公开(公告)号：US06716653B2

公开(公告)日：2004-04-06

申请号：US10280175

申请日：2002-10-24

Applicant: Kevin T. Look ,  Shih-Cheng Hsueh

Inventor： Kevin T. Look ,  Shih-Cheng Hsueh

IPC: G01R3126

CPC classification number: G03F7/70633 ,  G01B7/003 ,  H01L22/34

Abstract: An electrical alignment test structure enables monitoring and measuring misalignment between layers (or associated masks) of an IC. The alignment test structure comprises a target region and an alignment feature in different layers. The target region and the alignment feature may be formed in diffusion and polysilicon layers, respectively or in well and diffusion layers, respectively. In both embodiments, the alignment feature controls the size of a conductive channel in the target region. Misalignment can be checked by comparing channel resistance with a baseline (no misalignment) resistance. In another embodiment, the target region and alignment feature are formed in the diffusion and polysilicon layers, respectively, wherein the alignment feature controls the relative widths of the source and drain regions. Misalignment can be checked by comparing current flow with a baseline current. In another embodiment, the target and alignment regions are formed in the well and diffusion layers, respectively, to form a diode, wherein misalignment can be checked by comparing current flow through the alignment feature with a baseline current. Multiple test structures can be combined in an array in accordance with an embodiment of the invention. By configuring the test structures in two mirror-image sets, the array can measure the amount of misalignment between the well and diffusion layers.

Abstract translation: 电气对准测试结构能够监视和测量IC的层（或相关掩模）之间的未对准。 对准测试结构包括不同层中的目标区域和对准特征。 目标区域和对准特征可以分别形成在扩散层和多晶硅层中，或分别形成在阱层和扩散层中。 在两个实施例中，对准特征控制目标区域中的导电通道的尺寸。 可以通过比较通道电阻与基线（无对准）电阻来检查未对准。 在另一个实施例中，目标区域和对准特征分别形成在扩散层和多晶硅层中，其中对准特征控制源极和漏极区域的相对宽度。 可以通过将电流与基线电流进行比较来检查未对准。 在另一个实施例中，靶和对准区分别形成在阱和扩散层中以形成二极管，其中可以通过比较通过对准特征的电流与基线电流来检查未对准。 根据本发明的实施例，多个测试结构可以组合成阵列。 通过将测试结构配置在两个镜像组中，阵列可以测量阱和扩散层之间的未对准量。

公开(公告)号：US06684520B1

公开(公告)日：2004-02-03

申请号：US09514041

申请日：2000-02-25

Applicant: Kevin T. Look ,  Shih-Cheng Hsueh

Inventor： Kevin T. Look ,  Shih-Cheng Hsueh

IPC: G01D2100

CPC classification number: H01L22/34

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

Abstract translation: 描述了掩模对准检测结构，其测量使用电阻元件的集成电路的层之间的未对准的方向和程度，其中电阻随着一维中的未对准而变化。 根据本发明的测量对于工艺变化相对不敏感，并且用于进行这些测量的结构可以与使用标准工艺的集成电路上的其它特征一起形成。 本发明的一个实施例可用于测量两个导电层之间的未对准。 其他实施例测量扩散区域和导体之间以及扩散区域和窗口之间的未对准，通过该窗口将形成其他扩散区域。 根据一个实施例的电路包括行和列解码器，用于独立地选择掩模对准检测结构以减少实现检测结构所需的测试终端的数量。

公开(公告)号：US06569576B1

公开(公告)日：2003-05-27

申请号：US09672167

申请日：2000-09-27

Applicant: Shih-Cheng Hsueh ,  Kevin T. Look ,  Jonathan Jung-Ching Ho

Inventor： Shih-Cheng Hsueh ,  Kevin T. Look ,  Jonathan Jung-Ching Ho

IPC: G03F900

CPC classification number: G03F1/40 ,  G03F1/62

Abstract: A reticle and pellicle that are modified to prevent ESD damage to the masking material between portions of the lithographic mask pattern on the reticle during an integrated circuit fabrication process. The modification involves providing conducting lines on the glass side of the reticle and on the surface of the pellicle to balance any buildup of electrostatic charges on those devices, thereby reducing or eliminating the induction of opposite charges onto adjacent mask pattern features on the reticle and preventing the melting and bridging of those mask pattern features and the defects caused by such melting or bridging. The conductive metal lines may have a smaller width than the smallest resolution value of the reduction lens used in the mask pattern transfer process, and may also be located outside of the focal plane of the reduction lens to avoid transfer of the images of the conductive lines onto the target semiconductor substrate during the mask pattern transfer process.

Abstract translation: 在集成电路制造工艺期间，被修改以防止在掩模版上的光刻掩模图案的部分之间对掩模材料的ESD损伤的掩模版和防护薄膜。 该修改包括在掩模版的玻璃面和防护薄膜组件的表面上提供导线，以平衡这些装置上的静电电荷的积累，从而减少或消除相反电荷对掩模版上相邻掩模图案特征的诱导，并防止 这些掩模图案特征的熔化和桥接以及由这种熔融或桥接引起的缺陷。 导电金属线可以具有比在掩模图案转印工艺中使用的减少透镜的最小分辨率值更小的宽度，并且还可以位于缩小透镜的焦平面的外侧，以避免传导导线的图像 在掩模图案转印处理期间到达目标半导体衬底。

公开(公告)号：US06426534B1

公开(公告)日：2002-07-30

申请号：US09561785

申请日：2000-05-01

Applicant: Kevin T. Look ,  Shih-Cheng Hsueh

Inventor： Kevin T. Look ,  Shih-Cheng Hsueh

IPC: H01L31119

CPC classification number: H01L22/34

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit. Each structure includes one or more MOS transistors, each of which exhibits a threshold voltage that varies with misalignment in one dimension. The test structures are configured in mirrored pairs, so that misalignment in one direction oppositely affects the threshold voltages of the paired structures. The threshold voltages of the paired structures can therefore be compared to determine the extent and direction of misalignment. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between active implants and the windows in which active regions are formed. Other embodiments measure misalignment between threshold-voltage implants and-the active regions.

Abstract translation: 描述了测量集成电路的层之间的未对准的方向和程度的掩模对准检测结构。 每个结构包括一个或多个MOS晶体管，每个MOS晶体管表现出一个维度随着不对准而变化的阈值电压。 测试结构被配置成镜像对，使得在一个方向上的未对准相反地影响配对结构的阈值电压。 因此，可以比较成对结构的阈值电压以确定未对准的程度和方向。 根据本发明的测量对于工艺变化相对不敏感，并且用于进行这些测量的结构可以与使用标准工艺的集成电路上的其它特征一起形成。 本发明的一个实施例可用于测量活性植入物与其中形成活性区域的窗口之间的未对准。 其他实施例测量阈值电压植入物与活性区域之间的未对准。

公开(公告)号：US07032194B1

公开(公告)日：2006-04-18

申请号：US10369888

申请日：2003-02-19

Applicant: Shih-Cheng Hsueh ,  Xiao-Jie Yuan ,  Daniel Gitlin

Inventor： Shih-Cheng Hsueh ,  Xiao-Jie Yuan ,  Daniel Gitlin

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method for dealing with process specific physical effects applies dimensional modifications to an IC layout to compensate for performance variations caused by the physical effects. Because the dimensional modifications harmonize the performance of the actual IC with the performance of the IC model, time-consuming re-verification operations are not required. Current drive variations caused by shallow trench isolation (STI) stress can be compensated for by adjusting the gate dimensions of the affected transistors to increase or decrease current drive as necessary. Such physical effect compensation can be applied before, after, or even concurrently with optical proximity correction (OPC). The dimensional modifications for physical effect compensation can also be incorporated into an OPC engine.

Abstract translation: 处理过程特定物理效应的方法对IC布局进行尺寸修改以补偿由物理效应引起的性能变化。 由于尺寸修改使实际IC的性能与IC型号的性能相协调，因此不需要耗时的重新验证操作。 由浅沟槽隔离（STI）应力引起的电流驱动变化可以通过调整受影响的晶体管的栅极尺寸以根据需要增加或减少电流驱动来补偿。 这种物理效应补偿可以在光学邻近校正（OPC）之前，之后或甚至同时应用。 用于物理效应补偿的尺寸修改也可以并入到OPC引擎中。

公开(公告)号：US06563320B1

公开(公告)日：2003-05-13

申请号：US09738815

申请日：2000-12-15

Applicant: Kevin T. Look ,  Shih-Cheng Hsueh

Inventor： Kevin T. Look ,  Shih-Cheng Hsueh

IPC: G01R3108

CPC classification number: G03F7/70633 ,  G01B7/003 ,  H01L22/34

Abstract: An electrical alignment test structure enables monitoring and measuring misalignment between layers (or associated masks) of an IC. The alignment test structure comprises a target region and an alignment feature in different layers. The target region and the alignment feature may be formed in diffusion and polysilicon layers, respectively or in well and diffusion layers, respectively. In both embodiments, the alignment feature controls the size of a conductive channel in the target region. Misalignment can be checked by comparing channel resistance with a baseline (no misalignment) resistance. In another embodiment, the target region and alignment feature are formed in the diffusion and polysilicon layers, respectively, wherein the alignment feature controls the relative widths of the source and drain regions. Misalignment can be checked by comparing current flow with a baseline current. In another embodiment, the target and alignment regions are formed in the well and diffusion layers, respectively, to form a diode, wherein misalignment can be checked by comparing current flow through the alignment feature with a baseline current. Multiple test structures can be combined in an array in accordance with an embodiment of the invention. By configuring the test structures in two mirror-image sets, the array can measure the amount of misalignment between the well and diffusion layers.