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    Layout correction algorithms for removing stress and other physical effect induced process deviation
    1.
    发明授权
    Layout correction algorithms for removing stress and other physical effect induced process deviation 有权
    用于去除应力和其他物理效应的布局校正算法引起的过程偏差

    公开(公告)号：US07032194B1

    公开(公告)日：2006-04-18

    申请号：US10369888

    申请日：2003-02-19

    申请人： Shih-Cheng Hsueh ,  Xiao-Jie Yuan ,  Daniel Gitlin

    发明人： Shih-Cheng Hsueh ,  Xiao-Jie Yuan ,  Daniel Gitlin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method for dealing with process specific physical effects applies dimensional modifications to an IC layout to compensate for performance variations caused by the physical effects. Because the dimensional modifications harmonize the performance of the actual IC with the performance of the IC model, time-consuming re-verification operations are not required. Current drive variations caused by shallow trench isolation (STI) stress can be compensated for by adjusting the gate dimensions of the affected transistors to increase or decrease current drive as necessary. Such physical effect compensation can be applied before, after, or even concurrently with optical proximity correction (OPC). The dimensional modifications for physical effect compensation can also be incorporated into an OPC engine.

    摘要翻译： 处理过程特定物理效应的方法对IC布局进行尺寸修改以补偿由物理效应引起的性能变化。 由于尺寸修改使实际IC的性能与IC型号的性能相协调，因此不需要耗时的重新验证操作。 由浅沟槽隔离（STI）应力引起的电流驱动变化可以通过调整受影响的晶体管的栅极尺寸以根据需要增加或减少电流驱动来补偿。 这种物理效应补偿可以在光学邻近校正（OPC）之前，之后或甚至同时应用。 用于物理效应补偿的尺寸修改也可以并入到OPC引擎中。

    Characterizing circuit performance by separating device and interconnect impact on signal delay
    2.
    发明申请
    Characterizing circuit performance by separating device and interconnect impact on signal delay 有权

    公开(公告)号：US20060267618A1

    公开(公告)日：2006-11-30

    申请号：US11498371

    申请日：2006-08-03

    申请人： Xiao-Jie Yuan ,  Michael Hart ,  Zicheng Ling ,  Steven Young

    发明人： Xiao-Jie Yuan ,  Michael Hart ,  Zicheng Ling ,  Steven Young

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2882 ,  G01R31/318511 ,  G01R31/318516 ,  G01R31/3187

    摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

    Characterizing circuit performance by separating device and interconnect impact on signal delay
    3.
    发明授权
    Characterizing circuit performance by separating device and interconnect impact on signal delay 有权
    通过分离器件和互连对信号延迟的影响来表征电路性能

    公开(公告)号：US07489152B2

    公开(公告)日：2009-02-10

    申请号：US11498371

    申请日：2006-08-03

    申请人： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    发明人： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2882 ,  G01R31/318511 ,  G01R31/318516 ,  G01R31/3187

    摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

    摘要翻译： 集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。 测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。 为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。 然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。 最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。

    CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCONNECT IMPACT ON SIGNAL DELAY
    5.
    发明申请
    CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCONNECT IMPACT ON SIGNAL DELAY 失效
    通过分离设备来表征电路性能和对信号延迟的互连影响

    公开(公告)号：US20090121737A1

    公开(公告)日：2009-05-14

    申请号：US12355988

    申请日：2009-01-19

    申请人： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    发明人： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    IPC分类号： G01R31/26 ,  G01R31/02 ,  H01L23/58

    CPC分类号： G01R31/2882 ,  G01R31/318511 ,  G01R31/318516 ,  G01R31/3187

    摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

    摘要翻译： 集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。 测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。 为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。 然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。 最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。

    Characterizing circuit performance by separating device and interconnect impact on signal delay
    6.
    发明授权
    Characterizing circuit performance by separating device and interconnect impact on signal delay 失效
    通过分离器件和互连对信号延迟的影响来表征电路性能

    公开(公告)号：US07724016B2

    公开(公告)日：2010-05-25

    申请号：US12355988

    申请日：2009-01-19

    申请人： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    发明人： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2882 ,  G01R31/318511 ,  G01R31/318516 ,  G01R31/3187

    摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

    摘要翻译： 集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。 测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。 为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。 然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。 最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。

    Characterizing circuit performance by separating device and interconnect impact on signal delay
    7.
    发明申请
    Characterizing circuit performance by separating device and interconnect impact on signal delay 有权
    通过分离器件和互连对信号延迟的影响来表征电路性能

    公开(公告)号：US20050149777A1

    公开(公告)日：2005-07-07

    申请号：US10742300

    申请日：2003-12-18

    申请人： Xiao-Jie Yuan ,  Michael Hart ,  Zicheng Ling ,  Steven Young

    发明人： Xiao-Jie Yuan ,  Michael Hart ,  Zicheng Ling ,  Steven Young

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G01R31/3187 ,  G11B5/00 ,  G01R31/02 ,  G06K5/04 ,  G11B20/20

    CPC分类号： G01R31/2882 ,  G01R31/318511 ,  G01R31/318516 ,  G01R31/3187

    摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

    摘要翻译： 集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。 测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。 为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。 然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。 最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。