公开(公告)号：US08199157B2

公开(公告)日：2012-06-12

申请号：US12023916

申请日：2008-01-31

Applicant: Sun-Hee Park ,  Shin-Chan Kang

Inventor： Sun-Hee Park ,  Shin-Chan Kang

IPC: G06F13/14 ,  G09G5/39

CPC classification number: G06T1/20

Abstract: A system on chip (Soc) includes a system bus, a plurality of sub-systems, an image processing logic block, an image memory interface and an image processing memory block. The sub-systems are respectively connected to the system bus. The image processing logic block is connected to the system bus. The image processing logic block performs an image processing. The image processing logic block is included in a first power domain. The image memory interface is connected to the system bus and the image processing logic block. The image processing memory block is connected to the image memory interface. The image processing memory block is used for the image processing. The image memory interface and the image processing memory block are included in a second power domain different from the first power domain.

Abstract translation: 片上系统（Soc）包括系统总线，多个子系统，图像处理逻辑块，图像存储器接口和图像处理存储器块。 子系统分别连接到系统总线。 图像处理逻辑块连接到系统总线。 图像处理逻辑块执行图像处理。 图像处理逻辑块被包括在第一电源域中。 图像存储器接口连接到系统总线和图像处理逻辑块。 图像处理存储器块连接到图像存储器接口。 图像处理存储块用于图像处理。 图像存储器接口和图像处理存储器块包括在与第一功率域不同的第二功率域中。

公开(公告)号：US20100088564A1

公开(公告)日：2010-04-08

申请号：US12632856

申请日：2009-12-08

Applicant: Shin-Chan KANG ,  Sun-Kyu KIM

Inventor： Shin-Chan KANG ,  Sun-Kyu KIM

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G06F11/2236

Abstract: A semiconductor IC capable of debugging two or more processors at the same time by means of a single debugger and a semiconductor IC test system. The semiconductor IC includes processors operating at different frequencies, a trigger circuit which causes all of the processors to be in a debugging state when one of the processors is in the debugging state, and a JTAG circuit applying a boundary scan operation to the processors connected to a JTAG pin in series.

Abstract translation: 一种能够通过单个调试器和半导体IC测试系统同时调试两个或多个处理器的半导体IC。 半导体IC包括以不同频率工作的处理器，触发电路，当处理器中的一个处于调试状态时，使所有处理器处于调试状态，并且JTAG电路将边界扫描操作应用于连接到 串联的JTAG引脚。

公开(公告)号：US07707340B2

公开(公告)日：2010-04-27

申请号：US12219659

申请日：2008-07-25

Applicant: Shin-Chan Kang ,  Jae-Young Lee ,  Kyo-Keun Ku

Inventor： Shin-Chan Kang ,  Jae-Young Lee ,  Kyo-Keun Ku

IPC: G06F13/00 ,  G06F13/38 ,  G06F12/00 ,  G06F13/42

CPC classification number: G06F13/364

Abstract: A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB), at least one bus master device, a bus arbiter and at least one transfer mode selection circuit. The at least one bus master device may generate a burst cycle control signal, a transfer start signal and a bus control request signal for requesting control of the bus, and may be activated in response to a bus control grant signal, so as to exchange data via the bus. The bus arbiter may generate the bus control grant signal in response to the bus control request signal and provide the bus control grant signal to the bus master device. The at least one transfer mode selection circuit may convert a burst mode into a single mode to generate a selection signal, when the bus control grant signal is deactivated before a burst mode operation is completed.

Abstract translation: 当在突发模式期间发生提前终止时，可能阻止数据被错误传送的总线系统可以包括总线，例如高级高性能总线（AHB），至少一个总线主设备，总线仲裁器 和至少一个传送模式选择电路。 所述至少一个总线主设备可以产生突发周期控制信号，传输开始信号和用于请求总线控制的总线控制请求信号，并且可以响应于总线控制许可信号激活以便交换数据 通过公共汽车。 总线仲裁器可以响应总线控制请求信号产生总线控制授权信号，并向总线主设备提供总线控制授权信号。 当在突发模式操作完成之前总线控制授权信号被去激活时，至少一个传输模式选择电路可以将突发模式转换成单个模式以产生选择信号。

公开(公告)号：US07644310B2

公开(公告)日：2010-01-05

申请号：US12193945

申请日：2008-08-19

Applicant: Shin-Chan Kang ,  Sun-Kyu Kim

Inventor： Shin-Chan Kang ,  Sun-Kyu Kim

IPC: G06F11/00

CPC classification number: G06F11/2236

Abstract: A semiconductor IC capable of debugging two or more processors at the same time by means of a single debugger and a semiconductor IC test system. The semiconductor IC includes processors operating at different frequencies, a trigger circuit which causes all of the processors to be in a debugging state when one of the processors is in the debugging state, and a JTAG circuit applying a boundary scan operation to the processors connected to a JTAG pin in series.

Abstract translation: 一种能够通过单个调试器和半导体IC测试系统同时调试两个或多个处理器的半导体IC。 半导体IC包括以不同频率工作的处理器，触发电路，当处理器中的一个处于调试状态时，使所有处理器处于调试状态，并且JTAG电路将边界扫描操作应用于连接到 串联的JTAG引脚。

公开(公告)号：US08055946B2

公开(公告)日：2011-11-08

申请号：US12632856

申请日：2009-12-08

Applicant: Shin-Chan Kang ,  Sun-Kyu Kim

Inventor： Shin-Chan Kang ,  Sun-Kyu Kim

IPC: G06F11/00

CPC classification number: G06F11/2236

Abstract: A semiconductor IC capable of debugging two or more processors at the same time using a single debugger and a semiconductor IC test system. The semiconductor IC includes processors operating at different frequencies, a trigger circuit which causes all of the processors to be in a debugging state when one of the processors is in the debugging state, and a JTAG circuit applying a boundary scan operation to the processors connected to a JTAG pin in series.

Abstract translation: 一种能够使用单个调试器和半导体IC测试系统同时调试两个或多个处理器的半导体IC。 半导体IC包括以不同频率工作的处理器，触发电路，当处理器中的一个处于调试状态时，使所有处理器处于调试状态，并且JTAG电路将边界扫描操作应用于连接到 串联的JTAG引脚。

公开(公告)号：US20080307260A1

公开(公告)日：2008-12-11

申请号：US12193945

申请日：2008-08-19

Applicant: Shin-Chan KANG ,  Sun-Kyu KIM

Inventor： Shin-Chan KANG ,  Sun-Kyu KIM

IPC: G06F11/00

CPC classification number: G06F11/2236

Abstract: A semiconductor IC capable of debugging two or more processors at the same time by means of a single debugger and a semiconductor IC test system. The semiconductor IC includes processors operating at different frequencies, a trigger circuit which causes all of the processors to be in a debugging state when one of the processors is in the debugging state, and a JTAG circuit applying a boundary scan operation to the processors connected to a JTAG pin in series.

Abstract translation: 一种能够通过单个调试器和半导体IC测试系统同时调试两个或多个处理器的半导体IC。 半导体IC包括以不同频率工作的处理器，触发电路，当处理器中的一个处于调试状态时，使所有处理器处于调试状态，并且JTAG电路将边界扫描操作应用于连接到 串联的JTAG引脚。

公开(公告)号：US20080186321A1

公开(公告)日：2008-08-07

申请号：US12023916

申请日：2008-01-31

Applicant: Sun-hee Park ,  Shin-Chan Kang

Inventor： Sun-hee Park ,  Shin-Chan Kang

IPC: G06F12/06

CPC classification number: G06T1/20

Abstract: A system on chip (Soc) includes a system bus, a plurality of sub-systems, an image processing logic block, an image memory interface and an image processing memory block. The sub-systems are respectively connected to the system bus. The image processing logic block is connected to the system bus. The image processing logic block performs an image processing. The image processing logic block is included in a first power domain. The image memory interface is connected to the system bus and the image processing logic block. The image processing memory block is connected to the image memory interface. The image processing memory block is used for the image processing. The image memory interface and the image processing memory block are included in a second power domain different from the first power domain.

Abstract translation: 片上系统（Soc）包括系统总线，多个子系统，图像处理逻辑块，图像存储器接口和图像处理存储器块。 子系统分别连接到系统总线。 图像处理逻辑块被连接到系统总线。 图像处理逻辑块执行图像处理。 图像处理逻辑块被包括在第一电源域中。 图像存储器接口连接到系统总线和图像处理逻辑块。 图像处理存储器块连接到图像存储器接口。 图像处理存储块用于图像处理。 图像存储器接口和图像处理存储器块包括在与第一功率域不同的第二功率域中。

公开(公告)号：US07818527B2

公开(公告)日：2010-10-19

申请号：US11495026

申请日：2006-07-28

Applicant: Shin-Chan Kang

Inventor： Shin-Chan Kang

IPC: G06F13/00

CPC classification number: G11C7/10 ,  G06F13/4239

Abstract: A wrapper circuit effectively converts a muxed-type memory (having time-multiplexed address and data lines) into a non-muxed type memory as seen by the controller (a non-muxed type memory controller). Wrapper circuit includes a select circuit (e.g., multiplexer) and an input/output buffer. The select circuit receives write data and an address from a non-muxed type memory controller and selects either the write data or the address according to a first control signal. The input/output buffer receives the selection among the write data and the address and passes the write data or the address to a muxed type memory. The input/output buffer also passes read data received from the memory to the memory controller.

Abstract translation: 封装电路有效地将多路复用型存储器（具有时分多路复用地址和数据线）转换成非复用型存储器，如由控制器（非复用型存储器控制器）所见。 包装电路包括选择电路（例如，多路复用器）和输入/输出缓冲器。 选择电路从非复用型存储器控制器接收写入数据和地址，并根据第一控制信号选择写入数据或地址。 输入/输出缓冲器在写入数据和地址之间接收选择，并将写入数据或地址传递给多路复用型存储器。 输入/输出缓冲器还将从存储器接收的读取数据传送到存储器控制器。

公开(公告)号：US20080288688A1

公开(公告)日：2008-11-20

申请号：US12219659

申请日：2008-07-25

Applicant: Shin-Chan Kang ,  Jae-Young Lee ,  Kyo-Keun Ku

Inventor： Shin-Chan Kang ,  Jae-Young Lee ,  Kyo-Keun Ku

IPC: G06F13/00 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/364

Abstract: A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB), at least one bus master device, a bus arbiter and at least one transfer mode selection circuit. The at least one bus master device may generate a burst cycle control signal, a transfer start signal and a bus control request signal for requesting control of the bus, and may be activated in response to a bus control grant signal, so as to exchange data via the bus. The bus arbiter may generate the bus control grant signal in response to the bus control request signal and provide the bus control grant signal to the bus master device. The at least one transfer mode selection circuit may convert a burst mode into a single mode to generate a selection signal, when the bus control grant signal is deactivated before a burst mode operation is completed.

公开(公告)号：US07418535B2

公开(公告)日：2008-08-26

申请号：US11476839

申请日：2006-06-29

Applicant: Shin-Chan Kang ,  Jae-Young Lee ,  Kyo-Keun Ku

Inventor： Shin-Chan Kang ,  Jae-Young Lee ,  Kyo-Keun Ku

IPC: G06F13/00 ,  G06F13/38 ,  G06F12/00 ,  G06F13/42

CPC classification number: G06F13/364

Abstract: A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB), at least one bus master device, a bus arbiter and at least one transfer mode selection circuit. The at least one bus master device may generate a burst cycle control signal, a transfer start signal and a bus control request signal for requesting control of the bus, and may be activated in response to a bus control grant signal, so as to exchange data via the bus. The bus arbiter may generate the bus control grant signal in response to the bus control request signal and provide the bus control grant signal to the bus master device. The at least one transfer mode selection circuit may convert a burst mode into a single mode to generate a selection signal, when the bus control grant signal is deactivated before a burst mode operation is completed.

Abstract translation: 当在突发模式期间发生提前终止时，可能阻止数据被错误传送的总线系统可以包括总线，例如高级高性能总线（AHB），至少一个总线主设备，总线仲裁器 和至少一个传送模式选择电路。 所述至少一个总线主设备可以产生突发周期控制信号，传输开始信号和用于请求总线控制的总线控制请求信号，并且可以响应于总线控制许可信号激活以便交换数据 通过公共汽车。 总线仲裁器可以响应总线控制请求信号产生总线控制授权信号，并向总线主设备提供总线控制授权信号。 当在突发模式操作完成之前总线控制授权信号被去激活时，至少一个传输模式选择电路可以将突发模式转换成单个模式以产生选择信号。