User interface unit for fetching only active regions of a frame
    1.
    发明授权
    User interface unit for fetching only active regions of a frame 失效
    仅用于获取帧的活动区域的用户界面单元

    公开(公告)号:US08669993B2

    公开(公告)日:2014-03-11

    申请号:US12685152

    申请日:2010-01-11

    IPC分类号: G09G5/36 G06F13/00

    摘要: A user interface unit in a graphics processing display pipe may include registers programmable with information that defines active regions of an image frame. Pixels within the active regions of the image frame are meant to be displayed, while pixels outside of the active regions of the image frame are not to be displayed. Fetch circuitry within the user interface unit may fetch frames from memory, fetching only the pixels within the active regions of the image frames as defined by the programmed contents of the registers. The user interface unit may then provide the fetched pixels to a blend unit to blend the fetched pixels with pixels from other frames or pixels of a video stream to produce output frames. When blended with pixels of a video stream, the fetched pixels may be displayed as a graphics overlay on top of the video stream.

    摘要翻译: 图形处理显示管道中的用户界面单元可以包括可以定义图像帧的有效区域的信息来编程的寄存器。 旨在显示图像帧的有效区域内的像素,而不显示图像帧的有效区域之外的像素。 用户接口单元内的提取电路可以从存储器获取帧,仅获取由寄存器的编程内容定义的图像帧的有效区域内的像素。 然后,用户界面单元可以将获取的像素提供给混合单元,以将获取的像素与来自视频流的其他帧或像素的像素混合以产生输出帧。 当与视频流的像素混合时,获取的像素可以被显示为视频流顶部的图形覆盖。

    Buffer underrun handling
    2.
    发明授权
    Buffer underrun handling 有权
    缓冲区欠载处理

    公开(公告)号:US08675004B2

    公开(公告)日:2014-03-18

    申请号:US12685171

    申请日:2010-01-11

    IPC分类号: G06F13/372

    CPC分类号: G06T1/60 G09G5/39

    摘要: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.

    摘要翻译: 图形系统可以包括具有缓冲器的显示管道,缓冲器被配置为存储要由显示控制器处理的像素,用于在显示设备上显示,缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时,缓冲器控制电路检测到欠载,缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择,其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下,代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器,直到欠载已被解析为止,此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。

    Buffer Underrun Handling
    3.
    发明申请
    Buffer Underrun Handling 有权
    缓冲区欠载处理

    公开(公告)号:US20110169849A1

    公开(公告)日:2011-07-14

    申请号:US12685171

    申请日:2010-01-11

    IPC分类号: G09G5/36

    CPC分类号: G06T1/60 G09G5/39

    摘要: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.

    摘要翻译: 图形系统可以包括具有缓冲器的显示管道,缓冲器被配置为存储要由显示控制器处理的像素,用于在显示设备上显示,缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时,缓冲器控制电路检测到欠载,缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择,其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下,代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器,直到欠载已被解析为止,此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。

    Parameter FIFO
    4.
    发明申请
    Parameter FIFO 有权
    参数FIFO

    公开(公告)号:US20110169848A1

    公开(公告)日:2011-07-14

    申请号:US12685166

    申请日:2010-01-11

    IPC分类号: G09G5/36

    摘要: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

    摘要翻译: 图形系统可以包括用于处理当前显示帧的一个或多个处理单元,每个处理单元包括用于存储用于处理当前显示帧的参数设置的多个参数寄存器。 图形系统中的参数缓冲器可以存储帧分组,每个帧分组包含对应于要用于至少一个显示帧的参数设置的信息。 耦合到缓冲器和一个或多个处理单元的控制电路可以从参数缓冲器检索和处理顶部帧分组,以根据顶部帧分组的内容更新一个或多个参数寄存器。 控制电路可以发出DMA请求,用从系统存储器传送的帧分组填充参数缓冲器,其中帧分组可以由在中央处理单元上执行的应用(或软件)写入。

    User Interface Unit for Fetching Only Active Regions of a Frame
    5.
    发明申请
    User Interface Unit for Fetching Only Active Regions of a Frame 失效
    仅用于获取帧的活动区域的用户界面单元

    公开(公告)号:US20110169847A1

    公开(公告)日:2011-07-14

    申请号:US12685152

    申请日:2010-01-11

    IPC分类号: G09G5/36

    摘要: A user interface unit in a graphics processing display pipe may include registers programmable with information that defines active regions of an image frame. Pixels within the active regions of the image frame are meant to be displayed, while pixels outside of the active regions of the image frame are not to be displayed. Fetch circuitry within the user interface unit may fetch frames from memory, fetching only the pixels within the active regions of the image frames as defined by the programmed contents of the registers. The user interface unit may then provide the fetched pixels to a blend unit to blend the fetched pixels with pixels from other frames or pixels of a video stream to produce output frames. When blended with pixels of a video stream, the fetched pixels may be displayed as a graphics overlay on top of the video stream.

    摘要翻译: 图形处理显示管道中的用户界面单元可以包括可以定义图像帧的有效区域的信息来编程的寄存器。 旨在显示图像帧的有效区域内的像素,而不显示图像帧的有效区域之外的像素。 用户接口单元内的提取电路可以从存储器获取帧,仅获取由寄存器的编程内容定义的图像帧的有效区域内的像素。 然后,用户界面单元可以将获取的像素提供给混合单元,以将获取的像素与来自视频流的其他帧或像素的像素混合以产生输出帧。 当与视频流的像素混合时,获取的像素可以被显示为视频流顶部的图形覆盖。

    Parameter FIFO
    6.
    发明授权

    公开(公告)号:US08749568B2

    公开(公告)日:2014-06-10

    申请号:US12685166

    申请日:2010-01-11

    IPC分类号: G09G5/36

    摘要: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.