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公开(公告)号：US08749568B2
公开(公告)日：2014-06-10
申请号：US12685166
申请日：2010-01-11
IPC分类号： G09G5/36
CPC分类号： G06T1/60 , G09G5/14 , G09G5/363 , G09G2340/10 , G09G2360/12 , G09G2360/127
摘要： A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.
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公开(公告)号：US08669993B2
公开(公告)日：2014-03-11
申请号：US12685152
申请日：2010-01-11
CPC分类号： G06F3/14 , G09G5/14 , G09G5/397 , G09G2340/10 , G09G2360/12
摘要： A user interface unit in a graphics processing display pipe may include registers programmable with information that defines active regions of an image frame. Pixels within the active regions of the image frame are meant to be displayed, while pixels outside of the active regions of the image frame are not to be displayed. Fetch circuitry within the user interface unit may fetch frames from memory, fetching only the pixels within the active regions of the image frames as defined by the programmed contents of the registers. The user interface unit may then provide the fetched pixels to a blend unit to blend the fetched pixels with pixels from other frames or pixels of a video stream to produce output frames. When blended with pixels of a video stream, the fetched pixels may be displayed as a graphics overlay on top of the video stream.
摘要翻译： 图形处理显示管道中的用户界面单元可以包括可以定义图像帧的有效区域的信息来编程的寄存器。 旨在显示图像帧的有效区域内的像素，而不显示图像帧的有效区域之外的像素。 用户接口单元内的提取电路可以从存储器获取帧，仅获取由寄存器的编程内容定义的图像帧的有效区域内的像素。 然后，用户界面单元可以将获取的像素提供给混合单元，以将获取的像素与来自视频流的其他帧或像素的像素混合以产生输出帧。 当与视频流的像素混合时，获取的像素可以被显示为视频流顶部的图形覆盖。
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公开(公告)号：US08675004B2
公开(公告)日：2014-03-18
申请号：US12685171
申请日：2010-01-11
IPC分类号： G06F13/372
摘要： A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.
摘要翻译： 图形系统可以包括具有缓冲器的显示管道，缓冲器被配置为存储要由显示控制器处理的像素，用于在显示设备上显示，缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时，缓冲器控制电路检测到欠载，缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择，其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下，代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器，直到欠载已被解析为止，此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。
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公开(公告)号：US20110169849A1
公开(公告)日：2011-07-14
申请号：US12685171
申请日：2010-01-11
IPC分类号： G09G5/36
摘要： A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.
摘要翻译： 图形系统可以包括具有缓冲器的显示管道，缓冲器被配置为存储要由显示控制器处理的像素，用于在显示设备上显示，缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时，缓冲器控制电路检测到欠载，缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择，其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下，代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器，直到欠载已被解析为止，此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。
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公开(公告)号：US20110169848A1
公开(公告)日：2011-07-14
申请号：US12685166
申请日：2010-01-11
IPC分类号： G09G5/36
CPC分类号： G06T1/60 , G09G5/14 , G09G5/363 , G09G2340/10 , G09G2360/12 , G09G2360/127
摘要： A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.
摘要翻译： 图形系统可以包括用于处理当前显示帧的一个或多个处理单元，每个处理单元包括用于存储用于处理当前显示帧的参数设置的多个参数寄存器。 图形系统中的参数缓冲器可以存储帧分组，每个帧分组包含对应于要用于至少一个显示帧的参数设置的信息。 耦合到缓冲器和一个或多个处理单元的控制电路可以从参数缓冲器检索和处理顶部帧分组，以根据顶部帧分组的内容更新一个或多个参数寄存器。 控制电路可以发出DMA请求，用从系统存储器传送的帧分组填充参数缓冲器，其中帧分组可以由在中央处理单元上执行的应用（或软件）写入。
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公开(公告)号：US20110169847A1
公开(公告)日：2011-07-14
申请号：US12685152
申请日：2010-01-11
IPC分类号： G09G5/36
CPC分类号： G06F3/14 , G09G5/14 , G09G5/397 , G09G2340/10 , G09G2360/12
摘要： A user interface unit in a graphics processing display pipe may include registers programmable with information that defines active regions of an image frame. Pixels within the active regions of the image frame are meant to be displayed, while pixels outside of the active regions of the image frame are not to be displayed. Fetch circuitry within the user interface unit may fetch frames from memory, fetching only the pixels within the active regions of the image frames as defined by the programmed contents of the registers. The user interface unit may then provide the fetched pixels to a blend unit to blend the fetched pixels with pixels from other frames or pixels of a video stream to produce output frames. When blended with pixels of a video stream, the fetched pixels may be displayed as a graphics overlay on top of the video stream.
摘要翻译： 图形处理显示管道中的用户界面单元可以包括可以定义图像帧的有效区域的信息来编程的寄存器。 旨在显示图像帧的有效区域内的像素，而不显示图像帧的有效区域之外的像素。 用户接口单元内的提取电路可以从存储器获取帧，仅获取由寄存器的编程内容定义的图像帧的有效区域内的像素。 然后，用户界面单元可以将获取的像素提供给混合单元，以将获取的像素与来自视频流的其他帧或像素的像素混合以产生输出帧。 当与视频流的像素混合时，获取的像素可以被显示为视频流顶部的图形覆盖。
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公开(公告)号：US08749565B2
公开(公告)日：2014-06-10
申请号：US12950239
申请日：2010-11-19
IPC分类号： G06T1/60
CPC分类号： G09G5/397 , G09G5/36 , G09G2330/12 , G09G2340/0407 , G09G2340/06 , G09G2340/10 , G09G2340/125 , G09G2360/10 , G09G2360/125
摘要： Video display pipes may terminate with a FIFO (first-in first-out) buffer from which pixels are provided to a display controller to display the pixels on a graphics/video display. The display pipes may frequently process the pixels at a much higher rate than at which the display controller fetches the pixels from the FIFO buffer. In an error-checking only mode, the FIFO may be disabled, and an error-checking (e.g. CRC) block connected in front of the FIFO may receive the pixels processed by the display pipes as fast as the display pipes are capable of processing the pixels. Accordingly, the length of test/simulation time required to perform a test may be determined by the rate at which pixels are generated rather than the rate at which the display controller displays the pixels. It also becomes possible to perform testing/simulation in environments where a display is not supported or is not available. The results generated by the error-checking may be read and compared to an expected value to detect test pass/fail conditions.
摘要翻译： 视频显示管道可以用FIFO（先进先出）缓冲器终止，从而将像素提供给显示控制器以在图形/视频显示器上显示像素。 显示管道可以以比显示控制器从FIFO缓冲器提取像素的速率高得多的速率来频繁地处理像素。 在仅错误检查模式中，FIFO可以被禁用，并且连接在FIFO前面的错误校验（例如CRC）块可以像显示管能够处理显示管一样快地接收由显示管处理的像素 像素。 因此，执行测试所需的测试/模拟时间的长度可以由生成像素的速率而不是显示控制器显示像素的速率来确定。 在不支持显示或不可用的环境中也可以进行测试/模拟。 可以读取错误检查产生的结果并将其与期望值进行比较，以检测测试通过/失败条件。
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公开(公告)号：US08711170B2
公开(公告)日：2014-04-29
申请号：US13026559
申请日：2011-02-14
IPC分类号： G09G5/02
CPC分类号： G06T15/005 , G06T13/80 , G06T15/503
摘要： A video display pipe used for processing pixels of video and/or image frames may include edge Alpha registers for storing edge Alpha values corresponding to the edges of an image to be translated across a display screen. The edge Alpha values may be specified based on the fractional pixel value by which the image is to be moved in the current frame. The video pipe may copy the column and row of pixels that are in the direction of travel, and may apply the edge Alpha values to the copied column and row. The edge Alpha values may control blending of the additional column and row of the translated image with the adjacent pixels in the original frame, providing the effect of the partial pixel movement, simulating a sub-pixel rate of movement.
摘要翻译： 用于处理视频和/或图像帧的像素的视频显示管可以包括边缘Alpha寄存器，用于存储与通过显示屏幕翻译的图像的边缘相对应的边缘α值。 可以基于在当前帧中移动图像的分数像素值来指定边缘Alpha值。 视频管道可以复制行进方向的像素列和行，并且可以将边缘Alpha值应用于复制的列和行。 边缘Alpha值可以控制翻转图像的附加列和行与原始帧中的相邻像素的混合，从而提供部分像素移动的效果，模拟子像素移动速率。
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公开(公告)号：US20120206657A1
公开(公告)日：2012-08-16
申请号：US13026557
申请日：2011-02-14
申请人： Joseph P. Bratt , Peter F. Holland
发明人： Joseph P. Bratt , Peter F. Holland
IPC分类号： H04N9/64
CPC分类号： H04N9/646 , G06F7/584 , G09G2320/0271
摘要： A display pipe unit for processing pixels of video and/or image frames may be injected with dither-noise during processing of the pixels. A random noise generator implemented using Linear Feedback Shift Registers (LFSRs) produces pseudo-random numbers that are injected into the display pipe as dither-noise. Typically, such LFSRs shift freely during operation and the values of the LFSRs are used as needed. By shifting the LFSRs when the values are used to inject noise into newly received data, and not shifting the LFSRs when no new data is received, variations in the delays of receiving the data do not affect the pattern of noise applied to the frames. Therefore, dither-noise can be deterministically injected into the display pipe during testing/debug operation. By updating the LFSRs when new pixel data is available from the host interface instead of updating the LFSRs every cycle, the same dither-noise can be injected for the same received data.
摘要翻译： 用于处理视频和/或图像帧的像素的显示管单元可以在处理像素期间被注入抖动噪声。 使用线性反馈移位寄存器（LFSR）实现的随机噪声发生器产生作为抖动噪声注入显示管道的伪随机数。 通常，这样的LFSR在操作期间自由移动，并且根据需要使用LFSR的值。 当使用这些值将噪声注入到新接收到的数据中时，通过移位LFSR，并且在没有接收到新数据时不移动LFSR，接收数据的延迟的变化不影响施加到帧的噪声模式。 因此，在测试/调试操作期间，可以将抖动噪声确定性地注入显示管道。 当从主机接口获得新像素数据而不是每个周期更新LFSR时，通过更新LFSR，可以为相同的接收数据注入相同的抖动噪声。
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公开(公告)号：US20120206468A1
公开(公告)日：2012-08-16
申请号：US13026559
申请日：2011-02-14
IPC分类号： G09G5/36
CPC分类号： G06T15/005 , G06T13/80 , G06T15/503
摘要： A video display pipe used for processing pixels of video and/or image frames may include edge Alpha registers for storing edge Alpha values corresponding to the edges of an image to be translated across a display screen. The edge Alpha values may be specified based on the fractional pixel value by which the image is to be moved in the current frame. The video pipe may copy the column and row of pixels that are in the direction of travel, and may apply the edge Alpha values to the copied column and row. The edge Alpha values may control blending of the additional column and row of the translated image with the adjacent pixels in the original frame, providing the effect of the partial pixel movement, simulating a sub-pixel rate of movement.
摘要翻译： 用于处理视频和/或图像帧的像素的视频显示管可以包括边缘Alpha寄存器，用于存储与通过显示屏幕翻译的图像的边缘相对应的边缘α值。 可以基于在当前帧中移动图像的分数像素值来指定边缘Alpha值。 视频管道可以复制行进方向的像素列和行，并且可以将边缘Alpha值应用于复制的列和行。 边缘Alpha值可以控制翻转图像的附加列和行与原始帧中的相邻像素的混合，从而提供部分像素移动的效果，模拟子像素移动速率。
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