公开(公告)号：US20100187567A1

公开(公告)日：2010-07-29

申请号：US12656340

申请日：2010-01-26

Applicant: Hiromitsu Tanabe ,  Kenji Kouno ,  Yukio Tsuzuki ,  Shinji Amano

Inventor： Hiromitsu Tanabe ,  Kenji Kouno ,  Yukio Tsuzuki ,  Shinji Amano

IPC: H01L29/739

CPC classification number: H01L29/0834 ,  H01L29/0615 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/861 ,  H01L2924/0002 ,  H03K2217/0027 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface. A main region and a sensing region are formed on the first surface side of the semiconductor substrate. A RC-IGBT is formed in the main region and a sensing element for passing electric currents proportional to electric currents flowing through the RC-IGBT is formed in the sensing region. A collector region and a cathode region of the sensing element are formed on the second surface side of the semiconductor substrate. The collector region is located directly below the sensing region in a thickness direction of the semiconductor substrate. The cathode region is not located directly below the sensing region in the thickness direction.

Abstract translation: 半导体器件包括具有第一表面和第二表面的半导体衬底。 主区域和感测区域形成在半导体衬底的第一表面侧上。 在主区域中形成RC-IGBT，并且在感测区域中形成用于使电流与流过RC-IGBT的电流成比例的电流的感测元件。 感测元件的集电极区域和阴极区域形成在半导体衬底的第二表面侧上。 集电极区域位于半导体基板的厚度方向的感测区域正下方。 阴极区域不位于厚度方向的感测区域正下方。

公开(公告)号：US07045879B2

公开(公告)日：2006-05-16

申请号：US10744071

申请日：2003-12-24

Applicant: Yoshiyuki Hisada ,  Eiichi Okuno ,  Yoshihito Mitsuoka ,  Shinji Amano ,  Takeshi Endo ,  Shinichi Mukainakano ,  Ayahiko Ichimiya

Inventor： Yoshiyuki Hisada ,  Eiichi Okuno ,  Yoshihito Mitsuoka ,  Shinji Amano ,  Takeshi Endo ,  Shinichi Mukainakano ,  Ayahiko Ichimiya

IPC: H01L31/0312 ,  H01L31/036

CPC classification number: H01L29/7828 ,  H01L21/3247 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7838

Abstract: The principal surface of a p-type SiC substrate (1) is formed of a face intersecting (0001) Si-face at 10 to 16°. An n+ source region (2) and an n+ drain region (3) are formed in a surface layer portion at the principal surface of the p-type SiC substrate (1) so as to be separated from each other. A gate electrode (5) is formed on a gate oxide film (4) on the principal surface of the p-type SiC substrate (1).

Abstract translation: p型SiC衬底（1）的主表面由10-16度的与（0001）Si面相交的面形成。 在p型SiC衬底的主表面上的表面层部分形成有n + +源极区（2）和n + +漏极区（3） 1）以便彼此分离。 栅极电极（5）形成在p型SiC衬底（1）的主表面上的栅氧化膜（4）上。

公开(公告)号：US06482704B1

公开(公告)日：2002-11-19

申请号：US09714165

申请日：2000-11-17

Applicant: Shinji Amano ,  Eiichi Okuno ,  Tsuyoshi Yamamoto

Inventor： Shinji Amano ,  Eiichi Okuno ,  Tsuyoshi Yamamoto

IPC: H01L21336

CPC classification number: H01L21/049 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7828 ,  H01L29/7838

Abstract: In a method for manufacturing a silicon carbide semiconductor device including a gate oxide film formed on a surface channel layer, the gate oxide film is formed by a thermal oxidation treatment that is performed at conditions under which a recrystallization reaction between silicon dioxide (SiO2) and carbon (C) occurs to produce silicon carbide (SiC) with a Gibbs free energy G3 being negative. The recrystallization reaction is expressed by a chemical formula of SiO2+3C→SiC+2CO+G3. Accordingly, residual carbon can be reduced at an interface between the gate oxide film and the surface channel layer.

Abstract translation: 在制造包括形成在表面沟道层上的栅极氧化膜的碳化硅半导体器件的方法中，通过热氧化处理形成栅极氧化膜，所述热氧化处理在二氧化硅（SiO 2）和 碳（C）发生以产生具有吉布斯自由能G3的负极的碳化硅（SiC）。 再结晶反应用化学式SiO2 + 3C-> SiC + 2CO + G3表示。 因此，可以在栅极氧化膜和表面沟道层之间的界面处还原残留的碳。

公开(公告)号：US07616859B2

公开(公告)日：2009-11-10

申请号：US12155949

申请日：2008-06-12

Applicant: Norihito Tokura ,  Hiroki Sone ,  Shinji Amano ,  Hisato Kato

Inventor： Norihito Tokura ,  Hiroki Sone ,  Shinji Amano ,  Hisato Kato

IPC: G02B6/00

CPC classification number: H01L27/0664 ,  H01L29/407 ,  H01L29/7391 ,  H01L29/7397 ,  H01L29/861

Abstract: A semiconductor device includes a spaced-channel IGBT and an antiparallel diode that are formed in a same semiconductor substrate. The IGBT includes a base layer and insulated gate trenches by which the base layer is divided into a body region connected to an emitter and a floating region disconnected from the emitter. The IGBT is formed in a cell region of an IGBT region, and the diode is formed in a diode region. A boundary region of the IGBT region is located between the cell region and the diode region. A spacing between adjacent gate trenches in the boundary region is less than a spacing between adjacent gate trenches between which the floating region is located in the cell region.

Abstract translation: 半导体器件包括形成在同一半导体衬底中的间隔沟道IGBT和反并联二极管。 IGBT包括基极层和绝缘栅极沟槽，基极层被分成与发射极连接的主体区域和与发射极断开的浮动区域。 IGBT形成在IGBT区域的单元区域中，二极管形成在二极管区域中。 IGBT区域的边界区域位于单元区域和二极管区域之间。 边界区域中的相邻栅极沟槽之间的间隔小于相邻栅极沟槽之间的间隔，在该沟槽之间的浮动区域位于单元区域中。

公开(公告)号：US20070075798A1

公开(公告)日：2007-04-05

申请号：US11528472

申请日：2006-09-28

Applicant: Shinji Amano

Inventor： Shinji Amano

IPC: H03B5/08

CPC classification number: H03B5/1231 ,  H03B5/1212 ,  H03B5/1253 ,  H03B5/1265

Abstract: A voltage control oscillator that is provided to suitably receive digital broadcasting and is produced at low costs includes: a resonance circuit that includes variable capacitors, each having a capacitance controlling terminal, that are provided parallel to each other and are connected to an inductor, the circuit resonating at a resonant frequency that varies depending upon a sum of (i) an inductance of the inductor and (ii) capacitances of the variable capacitors; and at least one switch to determine what should be connected to at least one of said capacitance controlling terminals.

Abstract translation: 提供用于适当接收数字广播并以低成本生产的电压控制振荡器包括：谐振电路，其包括彼此并联并连接到电感器的各自具有电容控制端子的可变电容器， 谐振频率根据（i）电感器的电感和（ii）可变电容器的电容的和而变化的谐振频率谐振; 以及至少一个开关，用于确定应该连接到所述电容控制端子中的至少一个。

公开(公告)号：US6165822A

公开(公告)日：2000-12-26

申请号：US224351

申请日：1999-01-04

Applicant: Eiichi Okuno ,  Takeshi Endo ,  Shinji Amano

Inventor： Eiichi Okuno ,  Takeshi Endo ,  Shinji Amano

IPC: H01L29/16 ,  H01L21/04 ,  H01L29/04 ,  H01L29/06 ,  H01L29/12 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L21/335 ,  H01L21/338

CPC classification number: H01L29/0696 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A vertical type power MOSFET made of silicon carbide includes a surface channel layer doped with nitrogen as dopant with a concentration equal to or less than 1.times.10.sup.15 cm.sup.-3. Accordingly, when a gate oxide film is formed on the surface channel layer, an amount of silicon nitride produced in the gate oxide film and at the interface between the gate oxide film and the surface channel layer becomes extremely small. As a result, carrier traps are prevented from being produced by silicon nitride, resulting in stable FET characteristics and high reliability to the gate oxide film.

Abstract translation: 由碳化硅制成的垂直型功率MOSFET包括掺杂有氮作为掺杂剂的表面沟道层，其浓度等于或小于1×10 15 cm -3。 因此，当在表面沟道层上形成栅极氧化膜时，在栅极氧化膜中产生的氮化硅的量和栅氧化膜与表面沟道层之间的界面变得非常小。 结果，阻止了由氮化硅产生载流子阱，从而导致稳定的FET特性和对栅氧化膜的高可靠性。

公开(公告)号：US08242536B2

公开(公告)日：2012-08-14

申请号：US12656340

申请日：2010-01-26

Applicant: Hiromitsu Tanabe ,  Kenji Kouno ,  Yukio Tsuzuki ,  Shinji Amano

Inventor： Hiromitsu Tanabe ,  Kenji Kouno ,  Yukio Tsuzuki ,  Shinji Amano

IPC: H01L29/739

CPC classification number: H01L29/0834 ,  H01L29/0615 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/861 ,  H01L2924/0002 ,  H03K2217/0027 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface. A main region and a sensing region are formed on the first surface side of the semiconductor substrate. A RC-IGBT is formed in the main region and a sensing element for passing electric currents proportional to electric currents flowing through the RC-IGBT is formed in the sensing region. A collector region and a cathode region of the sensing element are formed on the second surface side of the semiconductor substrate. The collector region is located directly below the sensing region in a thickness direction of the semiconductor substrate. The cathode region is not located directly below the sensing region in the thickness direction.

Abstract translation: 半导体器件包括具有第一表面和第二表面的半导体衬底。 主区域和感测区域形成在半导体衬底的第一表面侧上。 在主区域中形成RC-IGBT，并且在感测区域中形成用于使电流与流过RC-IGBT的电流成比例的电流的感测元件。 感测元件的集电极区域和阴极区域形成在半导体衬底的第二表面侧上。 集电极区域位于半导体基板的厚度方向的感测区域正下方。 阴极区域不位于厚度方向的感测区域正下方。

公开(公告)号：US20090003496A1

公开(公告)日：2009-01-01

申请号：US12058840

申请日：2008-03-31

Applicant: Shinji AMANO

Inventor： Shinji AMANO

IPC: H04L1/00

CPC classification number: H04B1/28

Abstract: A reception apparatus is provided with a semiconductor integrated circuit device and a UHF-fixed band-pass filter provided in a stage preceding the semiconductor integrated circuit device. The semiconductor integrated circuit device includes a frequency converter, a to-be-frequency-converted-signal transmission line through which a to-be-frequency-converted signal is fed to the frequency converter, a local-oscillation-signal transmission line through which a local oscillation signal is fed to the frequency converter and an unnecessary-signal attenuation circuit, provided in the to-be-frequency-converted-signal transmission line, that attenuates an unnecessary signal included in signals transmitted through the to-be-frequency-converted-signal transmission line.

Abstract translation: 接收装置设置有半导体集成电路器件和设置在半导体集成电路器件之前的级中的UHF固定带通滤波器。 半导体集成电路装置包括频率转换器，频率转换信号传输线，频率转换信号通过该信号传输到变频器，本地振荡信号传输线，通过该本地振荡信号传输线 本地振荡信号被馈送到频率转换器，并且设置在待频率转换信号传输线中的不必要信号衰减电路，其衰减包括在通过频率转换信号传输的信号中发送的信号中的不必要信号， 转换信号传输线。

公开(公告)号：US20090001411A1

公开(公告)日：2009-01-01

申请号：US12155949

申请日：2008-06-12

Applicant: Norihito Tokura ,  Hiroki Sone ,  Shinji Amano ,  Hisato Kato

Inventor： Norihito Tokura ,  Hiroki Sone ,  Shinji Amano ,  Hisato Kato

IPC: H01L29/739

CPC classification number: H01L27/0664 ,  H01L29/407 ,  H01L29/7391 ,  H01L29/7397 ,  H01L29/861

Abstract: A semiconductor device includes a spaced-channel IGBT and an antiparalell diode that are formed in a same semiconductor substrate. The IGBT includes a base layer and insulated gate trenches by which the base layer is divided into a body region connected to an emitter and a floating region disconnected from the emitter. The IGBT is formed in a cell region of an IGBT region, and the diode is formed in a diode region. A boundary region of the IGBT region is located between the cell region and the diode region. A spacing between adjacent gate trenches in the boundary region is less than a spacing between adjacent gate trenches between which the floating region is located in the cell region.

Abstract translation: 半导体器件包括形成在同一半导体衬底中的间隔沟道IGBT和反分解二极管。 IGBT包括基极层和绝缘栅极沟槽，基极层被分成连接到发射极的体区和与发射极断开的浮动区域。 IGBT形成在IGBT区域的单元区域中，二极管形成在二极管区域中。 IGBT区域的边界区域位于单元区域和二极管区域之间。 边界区域中的相邻栅极沟槽之间的间隔小于相邻栅极沟槽之间的间隔，在该沟槽之间的浮动区域位于单元区域中。

公开(公告)号：US07155188B2

公开(公告)日：2006-12-26

申请号：US10255956

申请日：2002-09-27

Applicant: Mitsuhiro Noboru ,  Hiroshi Isoda ,  Shinji Amano

Inventor： Mitsuhiro Noboru ,  Hiroshi Isoda ,  Shinji Amano

IPC: H04B1/06 ,  H04B7/12 ,  H04B7/00 ,  H04B1/28

CPC classification number: H03L7/10 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/099

Abstract: Dispersing directions of oscillation frequency variable ranges of all voltage controlled oscillators provided in an integrated circuit are uniformed, and not only a range covering a frequency regardless of whether a dispersion occurs or not, but also a range covering the frequency only in a case where the dispersion occurs is used as the frequency variable range of the voltage controlled oscillator, and the frequency variable ranges of the voltage controlled oscillators are set so as to be successive with respect to each other, so that a small number of voltage controlled oscillators can cover a wide frequency variable range. Thus, the integrated circuit having voltage controlled oscillators therein is miniaturized.