公开(公告)号：US08232824B2

公开(公告)日：2012-07-31

申请号：US12688741

申请日：2010-01-15

Applicant: Chung-Hsing Wang ,  Chih-Chieh Chen ,  Chih Sheng Tsai ,  Shu Yi Ying

Inventor： Chung-Hsing Wang ,  Chih-Chieh Chen ,  Chih Sheng Tsai ,  Shu Yi Ying

IPC: H03K3/017

CPC classification number: H03K5/1565 ,  G06F1/04

Abstract: Circuits and methods for providing a pulsed clock signal for use with pulsed latch circuits are described. A variable pulse generator is coupled to form a pulsed clock output responsive to a control signal and a clock input signal. A feedback loop is provided with a pulse monitor and a pulse control circuit. Samples of the pulsed clock signal are taken by the pulse monitor and an output is formed in the form of a pattern. The pulse control circuit receives the output of the monitor and determines whether it matches a predetermined pattern. Adjustments are made to the control signal to adaptively adjust the pulsed clock signal. The feedback loop may operate continuously. In alternative embodiments the feedback loop may be powered down. Methods for adaptively controlling a pulsed clock signal are disclosed.

Abstract translation: 描述了提供用于脉冲锁存电路的脉冲时钟信号的电路和方法。 可变脉冲发生器耦合以响应于控制信号和时钟输入信号形成脉冲时钟输出。 反馈回路具有脉冲监视器和脉冲控制电路。 脉冲时钟信号的采样由脉冲监视器拍摄，并且以图案的形式形成输出。 脉冲控制电路接收监视器的输出并确定其是否匹配预定模式。 调整控制信号以自适应调整脉冲时钟信号。 反馈回路可以连续工作。 在替代实施例中，反馈回路可以断电。 公开了用于自适应地控制脉冲时钟信号的方法。

公开(公告)号：US07746142B2

公开(公告)日：2010-06-29

申请号：US12250224

申请日：2008-10-13

Applicant: Wei-Pin Changchein ,  Shu Yi Ying ,  Fu-Lung Hsueh

Inventor： Wei-Pin Changchein ,  Shu Yi Ying ,  Fu-Lung Hsueh

IPC: G06F1/04

CPC classification number: H03K19/00323 ,  G06F1/10

Abstract: Circuit and methods for automatic clock skew compensation in circuits having two power domains. When one of the power domains is operated with a lowered supply voltage, lowering the supply voltage tends to slow the clock pulse and produces clock skew. Circuitry is provided for selectively delaying the clock pulse in one of the power domains to reduce the clock skew by comparing the clock pulses, and then automatically delaying the clock pulse in one of the domains by a delay determined to minimize the skew. A method is provided where the clock skew between two clock pulses is determined and the delay needed in one of the clock pulses to reduce the skew is determined by sampling the clock skew using a plurality of delays at multiples of a minimum delay, and then automatically delaying the one clock pulse by selecting an appropriate delay. The method may be iterated.

Abstract translation: 具有两个电源域的电路中自动时钟偏移补偿的电路和方法。 当其中一个电源域以较低的电源电压工作时，降低电源电压会降低时钟脉冲并产生时钟偏移。 提供电路，用于选择性地延迟其中一个功率域中的时钟脉冲，以通过比较时钟脉冲来减小时钟偏移，然后自动延迟其中一个域中的时钟脉冲延迟确定的最小化偏差的延迟。 提供了一种方法，其中确定了两个时钟脉冲之间的时钟偏移，并且通过使用多个延迟以最小延迟的倍数对时钟偏差进行采样来确定在其中一个时钟脉冲中减少偏斜所需的延迟，然后自动地 通过选择适当的延迟来延迟一个时钟脉冲。 可以重复该方法。

公开(公告)号：US20100259308A1

公开(公告)日：2010-10-14

申请号：US12688741

申请日：2010-01-15

Applicant: Chung-Hsing Wang ,  Chih-Chieh Chen ,  Chih Sheng Tsai ,  Shu Yi Ying

Inventor： Chung-Hsing Wang ,  Chih-Chieh Chen ,  Chih Sheng Tsai ,  Shu Yi Ying

IPC: H03K3/017

CPC classification number: H03K5/1565 ,  G06F1/04

Abstract: Circuits and methods for providing a pulsed clock signal for use with pulsed latch circuits are described. A variable pulse generator is coupled to form a pulsed clock output responsive to a control signal and a clock input signal. A feedback loop is provided with a pulse monitor and a pulse control circuit. Samples of the pulsed clock signal are taken by the pulse monitor and an output is formed in the form of a pattern. The pulse control circuit receives the output of the monitor and determines whether it matches a predetermined pattern. Adjustments are made to the control signal to adaptively adjust the pulsed clock signal. The feedback loop may operate continuously. In alternative embodiments the feedback loop may be powered down. Methods for adaptively controlling a pulsed clock signal are disclosed.

Abstract translation: 描述了提供用于脉冲锁存电路的脉冲时钟信号的电路和方法。 可变脉冲发生器耦合以响应于控制信号和时钟输入信号形成脉冲时钟输出。 反馈回路具有脉冲监视器和脉冲控制电路。 脉冲时钟信号的采样由脉冲监视器拍摄，并且以图案的形式形成输出。 脉冲控制电路接收监视器的输出并确定其是否匹配预定模式。 调整控制信号以自适应调整脉冲时钟信号。 反馈回路可以连续工作。 在替代实施例中，反馈回路可以断电。 公开了用于自适应地控制脉冲时钟信号的方法。

公开(公告)号：US20100090738A1

公开(公告)日：2010-04-15

申请号：US12250224

申请日：2008-10-13

Applicant: Wei-Pin Changchein ,  Shu Yi Ying ,  Fu-Lung Hsueh

Inventor： Wei-Pin Changchein ,  Shu Yi Ying ,  Fu-Lung Hsueh

IPC: H03K5/12

CPC classification number: H03K19/00323 ,  G06F1/10

Abstract: Circuit and methods for automatic clock skew compensation in circuits having two power domains. When one of the power domains is operated with a lowered supply voltage, lowering the supply voltage tends to slow the clock pulse and produces clock skew. Circuitry is provided for selectively delaying the clock pulse in one of the power domains to reduce the clock skew by comparing the clock pulses, and then automatically delaying the clock pulse in one of the domains by a delay determined to minimize the skew. A method is provided where the clock skew between two clock pulses is determined and the delay needed in one of the clock pulses to reduce the skew is determined by sampling the clock skew using a plurality of delays at multiples of a minimum delay, and then automatically delaying the one clock pulse by selecting an appropriate delay. The method may be iterated.

Abstract translation: 具有两个电源域的电路中自动时钟偏移补偿的电路和方法。 当其中一个电源域以较低的电源电压工作时，降低电源电压会降低时钟脉冲并产生时钟偏移。 提供电路，用于选择性地延迟其中一个功率域中的时钟脉冲，以通过比较时钟脉冲来减小时钟偏移，然后自动延迟其中一个域中的时钟脉冲延迟确定的最小化偏差的延迟。 提供了一种方法，其中确定了两个时钟脉冲之间的时钟偏移，并且通过使用多个延迟以最小延迟的倍数对时钟偏差进行采样来确定在其中一个时钟脉冲中减少偏斜所需的延迟，然后自动地 通过选择适当的延迟来延迟一个时钟脉冲。 可以重复该方法。

公开(公告)号：US20110035717A1

公开(公告)日：2011-02-10

申请号：US12846594

申请日：2010-07-29

Applicant: Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu Alex Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

Inventor： Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu Alex Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5072

Abstract: An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

Abstract translation: 本发明的实施例是一种用于提供集成电路布局的经调整的电子表示的计算机程序产品。 计算机程序产品具有其上体现计算机程序的介质。 此外，计算机程序包括用于从完整节点网表提供全节点单元的计算机程序代码，用于缩放全节点单元以提供收缩节点单元的计算机程序代码，用于提供全节点单元的定时性能的计算机程序代码和 收缩节点单元，用于将全节点单元的定时性能与收缩节点单元的定时性能进行比较的计算机程序代码以及用于提供第一网表的计算机程序代码。

公开(公告)号：US09672315B2

公开(公告)日：2017-06-06

申请号：US12846594

申请日：2010-07-29

Applicant: Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu “Alex” Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

Inventor： Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu “Alex” Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5072

Abstract: An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.