公开(公告)号：US08674355B2

公开(公告)日：2014-03-18

申请号：US12980865

申请日：2010-12-29

Applicant: Huan-Chi Tseng ,  Heng-Hsin Liu ,  Shu-Cheng Kuo ,  Chien-Chang Lee ,  Chun-Hung Lin

Inventor： Huan-Chi Tseng ,  Heng-Hsin Liu ,  Shu-Cheng Kuo ,  Chien-Chang Lee ,  Chun-Hung Lin

IPC: H01L23/58

CPC classification number: H01L23/544 ,  H01L22/34 ,  H01L23/4824 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.

Abstract translation: 一种装置包括在模具中的测试单元。 测试单元包括物理测试区域，该物理测试区域包括有源区域和在该有源区域上并且彼此平行的多个导电线。 多个导线具有基本上均匀的间隔，其中没有接触插塞直接在多个导线上并连接到多个导线。 测试单元还包括电测试区域，该电测试区域包括晶体管，该晶体管具有由相同材料形成的栅极，并且处于与多个导线相同的电平; 以及连接到晶体管的源极，漏极和栅极的接触插塞。 测试单元还包括邻近物理测试区域和电测试区域的对准标记。

公开(公告)号：US20120168751A1

公开(公告)日：2012-07-05

申请号：US12980865

申请日：2010-12-29

Applicant: Huan-Chi Tseng ,  Heng-Hsin Liu ,  Shu-Cheng Kuo ,  Chien-Chang Lee ,  Chun-Hung Lin

Inventor： Huan-Chi Tseng ,  Heng-Hsin Liu ,  Shu-Cheng Kuo ,  Chien-Chang Lee ,  Chun-Hung Lin

IPC: H01L23/58

CPC classification number: H01L23/544 ,  H01L22/34 ,  H01L23/4824 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.

Abstract translation: 一种装置包括在模具中的测试单元。 测试单元包括物理测试区域，该物理测试区域包括有源区域和在该有源区域上并且彼此平行的多个导电线。 多个导线具有基本上均匀的间隔，其中没有接触插塞直接在多个导线上并连接到多个导线。 测试单元还包括电测试区域，该电测试区域包括晶体管，该晶体管具有由相同材料形成的栅极，并且处于与多个导线相同的电平; 以及连接到晶体管的源极，漏极和栅极的接触插塞。 测试单元还包括邻近物理测试区域和电测试区域的对准标记。