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公开(公告)号：US09151798B2
公开(公告)日：2015-10-06
申请号：US13192938
申请日：2011-07-28
申请人： Jhih Jie Shao , Tang-Hsuan Chung , Szu-Chia Huang , Huan Chi Tseng , Chien-Chang Lee , Yu-Lan Hsiao
发明人： Jhih Jie Shao , Tang-Hsuan Chung , Szu-Chia Huang , Huan Chi Tseng , Chien-Chang Lee , Yu-Lan Hsiao
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185
CPC分类号： G01R31/2889 , G01R31/2601 , G01R31/318511 , G01R31/318558 , G01R31/318572
摘要： Provided is an apparatus for testing a semiconductor device. The apparatus includes a plurality of testing pads. The apparatus includes a plurality of testing units. The apparatus includes a switching circuit coupled between the testing pads and the testing units. The switching circuit contains a plurality of switching devices. The apparatus includes a control circuit coupled to the switching circuit. The control circuit is operable to establish electrical coupling between a selected testing unit and one or more of the testing pads by selectively activating a subset of the switching devices.
摘要翻译： 提供了一种用于测试半导体器件的装置。 该装置包括多个测试垫。 该装置包括多个测试单元。 该装置包括耦合在测试焊盘和测试单元之间的开关电路。 开关电路包含多个开关器件。 该装置包括耦合到开关电路的控制电路。 控制电路可操作以通过选择性地激活开关装置的子集来建立所选择的测试单元与一个或多个测试焊盘之间的电耦合。
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公开(公告)号：US20130015877A1
公开(公告)日：2013-01-17
申请号：US13183962
申请日：2011-07-15
IPC分类号： G01R31/26
CPC分类号： G01R31/26 , G01R31/2607 , G01R31/275
摘要： The present disclosure provides a method for testing a semiconductor device. The method includes providing a testing unit and an electronic circuit coupled to the testing unit and applying a first electrical signal to the testing unit. The method includes sweeping a second electrical signal across a range of values, the second electrical signal supplying power to the electronic circuit, wherein the sweeping is performed while a value of the first electrical signal remains the same. The method includes measuring a third electrical signal during the sweeping, the measured third electrical signal having a range of values that each correspond to one of the values of the second electrical signal. The method includes adopting an optimum value of the second electrical signal that yields a minimum value of the third electrical signal. The method includes testing the testing unit while the second electrical signal is set to the optimum value.
摘要翻译： 本公开提供了一种用于测试半导体器件的方法。 该方法包括提供耦合到测试单元的测试单元和电子电路，并向测试单元施加第一电信号。 该方法包括跨越一定范围的值扫描第二电信号，第二电信号向电子电路供电，其中在第一电信号的值保持相同时进行扫描。 该方法包括在扫描期间测量第三电信号，所测量的第三电信号具有各自对应于第二电信号中的一个值的值的范围。 该方法包括采用产生第三电信号的最小值的第二电信号的最佳值。 该方法包括测试单元，而第二电信号被设置为最佳值。
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公开(公告)号：US06844626B2
公开(公告)日：2005-01-18
申请号：US10444229
申请日：2003-05-23
申请人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
发明人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
IPC分类号： H01L21/28 , H01L21/44 , H01L21/60 , H01L21/768 , H01L23/48 , H01L23/485 , H01L23/52 , H01L29/40
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05006 , H01L2224/05624 , H01L2224/05647 , H01L2224/13007 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01073 , H01L2924/01082 , H01L2924/01083 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043
摘要： A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.
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4.发明授权System for in-line monitoring of photo processing tilt in VLSI fabrication 有权用于在VLSI制造中在线监控照片处理去焦和图像倾斜的系统
公开(公告)号：US5990567A
公开(公告)日：1999-11-23
申请号：US262311
申请日：1999-03-04
CPC分类号： G03F7/70641 , H01L22/34
摘要： An integrated de-focus pattern provides an effective in-line monitor for photo processing steps of integrated circuit wafers. The de-focus pattern is formed on an integrated circuit wafer in the vertical and horizontal spaces between integrated circuit chips. The de-focus pattern has a number of different test patterns at different heights above the wafer surface. De-focus patterns are placed across the entire wafer surface. The de-focus patterns are formed at the same time the features of the circuit chips are formed. The de-focus patterns can be analyzed optically or using a scanning electron microscope.
摘要翻译： 集成的去焦点图案为集成电路晶片的照相处理步骤提供了有效的在线监视器。 在集成电路芯片之间的垂直和水平空间中的集成电路晶片上形成去焦图案。 去焦图案在晶片表面上方的不同高度具有许多不同的测试图案。 去焦点图案放置在整个晶片表面上。 在形成电路芯片的特征的同时形成去焦图形。 去焦图案可以光学分析或使用扫描电子显微镜。
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公开(公告)号：US20050081824A1
公开(公告)日：2005-04-21
申请号：US10689430
申请日：2003-10-20
申请人： Hong-Miao Chen , Yu-Chang Jong , Huan-Chi Tseng
发明人： Hong-Miao Chen , Yu-Chang Jong , Huan-Chi Tseng
IPC分类号： B08B6/00 , B08B7/00 , C25F1/00 , C25F3/30 , C25F5/00 , F02D1/00 , H01L21/02 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： B08B7/0042 , H01L21/02046 , Y10S438/906
摘要： The invention describes how contaminant particles may be removed from a surface without in any way damaging that surface. First, the positional co-ordinates of all particles on the surface are recorded. Optionally, only particles that can be expected to cause current or future damage to the surface are included. Then, using optical tweezers, each particle is individually removed and then disposed of. Six different ways to remove and dispose of particles are described.
摘要翻译： 本发明描述了如何从表面去除污染物颗粒，而不会以任何方式损坏该表面。 首先，记录表面上所有颗粒的位置坐标。 可选地，仅包括可以预期会对表面造成当前或未来损害的颗粒。 然后，使用光学镊子，分别除去每个颗粒，然后处理。 描述了去除和处理颗粒的六种不同的方法。
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6.发明授权
公开(公告)号：US5949547A
公开(公告)日：1999-09-07
申请号：US803352
申请日：1997-02-20
CPC分类号： G03F7/70641 , H01L22/34
摘要： An integrated de-focus pattern provides an effective in-line monitor of de-focus and relative tilt for photo processing steps of integrated circuit wafers. The de-focus pattern is formed on an integrated circuit wafer in the vertical and horizontal spaces between integrated circuit chips. The de-focus pattern has a number of different test patterns at different heights above the wafer surface. De-focus patterns are placed across the entire wafer surface. The de-focus patterns are formed at the same time the features of the circuit chips are formed. The de-focus patterns can be analyzed optically or using a scanning electron microscope.
摘要翻译： 集成的去焦点图案提供集成电路晶片的照相处理步骤的脱焦和相对倾斜的有效的在线监视器。 在集成电路芯片之间的垂直和水平空间中的集成电路晶片上形成去焦图案。 去焦图案在晶片表面上方的不同高度具有许多不同的测试图案。 去焦点图案放置在整个晶片表面上。 在形成电路芯片的特征的同时形成去焦图形。 去焦图案可以光学分析或使用扫描电子显微镜。
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公开(公告)号：US20130057306A1
公开(公告)日：2013-03-07
申请号：US13225816
申请日：2011-09-06
CPC分类号： G01R31/3004 , G01R31/025 , G01R31/30
摘要： The present disclosure provides a method for testing a semiconductor device. The method includes providing a test unit and an electronic circuit that is electrically coupled to the test unit. The method includes performing a multi-dimensional sweeping process. The multi-dimensional sweeping process includes sweeping a plurality of different electrical parameters across their respective ranges. The method includes monitoring a performance of the electronic circuit during the multi-dimensional sweeping process. The monitoring includes identifying optimum values of the different electrical parameters that yield a satisfactory performance of the electronic circuit. The method includes testing the test unit using the optimum values of the different electrical parameters.
摘要翻译： 本公开提供了一种用于测试半导体器件的方法。 该方法包括提供测试单元和电耦合到测试单元的电子电路。 该方法包括执行多维扫描处理。 多维扫描过程包括在其各自的范围内扫描多个不同的电参数。 该方法包括在多维扫描过程中监视电子电路的性能。 监测包括识别产生电子电路令人满意的性能的不同电参数的最佳值。 该方法包括使用不同电参数的最佳值测试测试单元。
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公开(公告)号：US09459316B2
公开(公告)日：2016-10-04
申请号：US13225816
申请日：2011-09-06
CPC分类号： G01R31/3004 , G01R31/025 , G01R31/30
摘要： The present disclosure provides a method for testing a semiconductor device. The method includes providing a test unit and an electronic circuit that is electrically coupled to the test unit. The method includes performing a multi-dimensional sweeping process. The multi-dimensional sweeping process includes sweeping a plurality of different electrical parameters across their respective ranges. The method includes monitoring a performance of the electronic circuit during the multi-dimensional sweeping process. The monitoring includes identifying optimum values of the different electrical parameters that yield a satisfactory performance of the electronic circuit. The method includes testing the test unit using the optimum values of the different electrical parameters.
摘要翻译： 本公开提供了一种用于测试半导体器件的方法。 该方法包括提供测试单元和电耦合到测试单元的电子电路。 该方法包括执行多维扫描处理。 多维扫描过程包括在其各自的范围内扫描多个不同的电参数。 该方法包括在多维扫描过程中监视电子电路的性能。 监测包括识别产生电子电路令人满意的性能的不同电参数的最佳值。 该方法包括使用不同电参数的最佳值测试测试单元。
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公开(公告)号：US08531201B2
公开(公告)日：2013-09-10
申请号：US13183962
申请日：2011-07-15
CPC分类号： G01R31/26 , G01R31/2607 , G01R31/275
摘要： The present disclosure provides a method for testing a semiconductor device. The method includes providing a testing unit and an electronic circuit coupled to the testing unit and applying a first electrical signal to the testing unit. The method includes sweeping a second electrical signal across a range of values, the second electrical signal supplying power to the electronic circuit, wherein the sweeping is performed while a value of the first electrical signal remains the same. The method includes measuring a third electrical signal during the sweeping, the measured third electrical signal having a range of values that each correspond to one of the values of the second electrical signal. The method includes adopting an optimum value of the second electrical signal that yields a minimum value of the third electrical signal. The method includes testing the testing unit while the second electrical signal is set to the optimum value.
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公开(公告)号：US08499274B2
公开(公告)日：2013-07-30
申请号：US13403289
申请日：2012-02-23
CPC分类号： G06F17/5022
摘要： A tool includes one or more machine readable storage mediums encoded with data. The data include a list of standard cells included in an integrated circuit (IC) design The data include a nominal leakage value approximating a respective median leakage value for each of the plurality of standard cells at a predetermined temperature and voltage. The data include at least one table including adjustment factors for calculating leakage based on voltage, temperature and process variations. The table includes a respective statistical scaling factor, for computing a mean leakage corresponding to a given median leakage. A processor is programmed to calculate and output a total IC leakage for the IC design at an input voltage and input temperature, based on the list, the nominal leakage values, the input voltage, the input temperature and at least one of the adjustment factors.
摘要翻译： 工具包括用数据编码的一个或多个机器可读存储介质。 数据包括集成电路（IC）设计中包括的标准单元的列表。数据包括在预定温度和电压下接近多个标准单元中的每一个的相应中值泄漏值的标称泄漏值。 数据包括至少一个表，其中包括基于电压，温度和过程变化来计算泄漏的调整因子。 该表包括相应的统计缩放因子，用于计算对应于给定中位泄漏的平均泄漏。 处理器被编程为基于列表，标称泄漏值，输入电压，输入温度和至少一个调整因子来计算并输出IC设计中的IC设计的总IC泄漏，输入电压和输入温度。
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