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    Tool Induced Shift Reduction Determination for Overlay Metrology
    1.
    发明申请
    Tool Induced Shift Reduction Determination for Overlay Metrology 有权
    刀具诱导换位测量用于覆盖计量学

    公开(公告)号：US20130286395A1

    公开(公告)日：2013-10-31

    申请号：US13457832

    申请日：2012-04-27

    Applicant: Yung-Yao Lee ,  Ying Ying Wang ,  Heng-Hsin Liu ,  Heng-Jen Lee

    Inventor： Yung-Yao Lee ,  Ying Ying Wang ,  Heng-Hsin Liu ,  Heng-Jen Lee

    IPC: G01B11/00

    CPC classification number: G01B11/00 ,  G03F7/70633

    Abstract: One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements.

    Abstract translation: 一个实施例涉及一种用于半导体工件加工的方法。 在该方法中，通过在第一半导体工件上执行TIS测量的基线数量来测量基线工具诱发位移（TIS）。 在确定基线TIS之后，该方法基于在第一后续半导体工件上进行的随后的TIS测量数确定随后的TIS。 随后的TIS测量数量小于TIS测量的基线数量。

    Litho Cluster and Modulization to Enhance Productivity
    2.
    发明申请
    Litho Cluster and Modulization to Enhance Productivity 有权
    Litho集群和模块化以提高生产力

    公开(公告)号：US20130252175A1

    公开(公告)日：2013-09-26

    申请号：US13429921

    申请日：2012-03-26

    Applicant: I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

    Inventor： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

    IPC: G03F7/20 ,  H01L21/00

    CPC classification number: G03F7/30 ,  G03F7/16 ,  G03F7/70991 ,  H01L21/67225 ,  H01L21/67745

    Abstract: The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

    Abstract translation: 本公开涉及一种用于半导体工件加工的平版印刷工具装置。 光刻工具装置将光刻工具组合成簇，并且将半导体工件在第一簇中的第一类型的多个光刻工具之间选择性地传输到第二簇中的第二类型的光刻工具。 通过转移组件实现选择性转移，转移组件耦合到识别第一类型的光刻工具中产生的缺陷的缺陷扫描工具。 所公开的平版印刷工具装置还利用共同的结构元件，例如壳体组件和诸如气体和化学品的共享功能元件。 光刻工具装置可以包括被配置成提供这些各种部件的模块化的烘烤，涂覆，曝光和显影单元，以便为给定的光刻制造工艺优化产量和效率。

    WAFER EDGE EXPOSURE UNIT
    4.
    发明申请
    WAFER EDGE EXPOSURE UNIT 有权
    WAFER EDGE曝光单元

    公开(公告)号：US20100285399A1

    公开(公告)日：2010-11-11

    申请号：US12437776

    申请日：2009-05-08

    Applicant: Po-Chang Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee

    Inventor： Po-Chang Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee

    IPC: G03F7/20 ,  G03B27/62

    CPC classification number: G03B27/62 ,  G03F7/70425

    Abstract: A wafer edge exposure unit comprises a chuck for supporting a wafer. The chuck is rotatable about a central axis. A plurality of light sources are positioned or movably positionable with a common radial distance from the axis of the rotatable chuck, each light source configured to direct exposure light on a respective edge portion of the wafer simultaneously.

    Abstract translation: 晶片边缘曝光单元包括用于支撑晶片的卡盘。 卡盘可绕中心轴线旋转。 多个光源以可旋转卡盘的轴线的公共径向距离定位或可移动地定位，每个光源被配置为将曝光光同时引导到晶片的相应边缘部分。

    Method of monitoring and controlling a silicon nitride etch step
    7.
    发明授权
    Method of monitoring and controlling a silicon nitride etch step 失效
    监测和控制氮化硅蚀刻步骤的方法

    公开(公告)号：US5639342A

    公开(公告)日：1997-06-17

    申请号：US616416

    申请日：1996-03-15

    Applicant: Sen Fu Chen ,  Wen Cheng Chang ,  Heng Hsin Liu ,  Bao Ru Yang

    Inventor： Sen Fu Chen ,  Wen Cheng Chang ,  Heng Hsin Liu ,  Bao Ru Yang

    IPC: H01L21/311 ,  H01L21/66 ,  H01L21/00

    CPC classification number: H01L22/24 ,  H01L21/31105 ,  H01L22/20

    Abstract: A patterned silicon nitride layer formed over a semiconductor integrated circuit wafer having a layer of pad oxide is often used as a mask for subsequent processing steps. Etching of the silicon nitride layer is difficult to control and can create defects in the pad oxide layer which are difficult to detect before the manufacture of the semiconductor integrated circuit wafer is completed. A method is described using potassium hydroxide treatment and scanning electron microscope evaluation of a test wafer for detection of defects at the silicon nitride etching step. Continued processing of defective wafers can be terminated and the silicon nitride etching step can be controlled using this method.

    Abstract translation: 在具有垫氧化物层的半导体集成电路晶片上形成的图案化氮化硅层经常用作后续处理步骤的掩模。 氮化硅层的蚀刻难以控制，并且可能在半导体集成电路晶片的制造完成之前在衬垫氧化物层中产生难以检测的缺陷。 使用氢氧化钾处理和扫描电子显微镜评价在氮化硅蚀刻步骤中检测缺陷的测试晶片的方法。 可以终止对缺陷晶片的继续处理，并且可以使用该方法来控制氮化硅蚀刻步骤。

    Tool induced shift reduction determination for overlay metrology
    10.
    发明授权
    Tool induced shift reduction determination for overlay metrology 有权
    刀具诱导移位减少确定重叠度量

    公开(公告)号：US08860941B2

    公开(公告)日：2014-10-14

    申请号：US13457832

    申请日：2012-04-27

    Applicant: Yung-Yao Lee ,  Ying Ying Wang ,  Heng-Hsin Liu ,  Heng-Jen Lee

    Inventor： Yung-Yao Lee ,  Ying Ying Wang ,  Heng-Hsin Liu ,  Heng-Jen Lee

    IPC: G01B11/00

    CPC classification number: G01B11/00 ,  G03F7/70633

    Abstract: One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements.

    Abstract translation: 一个实施例涉及一种用于半导体工件加工的方法。 在该方法中，通过在第一半导体工件上执行TIS测量的基线数量来测量基线工具诱发位移（TIS）。 在确定基线TIS之后，该方法基于在第一后续半导体工件上进行的随后的TIS测量数确定随后的TIS。 随后的TIS测量数量小于TIS测量的基线数量。

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