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公开(公告)号：US11978526B2
公开(公告)日：2024-05-07
申请号：US17705415
申请日：2022-03-28
申请人： Skymizer Taiwan Inc.
发明人： Shu-Ming Liu , Kai-Chiang Wu , Chien-Fa Chen , Wen Li Tang
CPC分类号： G11C29/4401 , G11C11/54 , G11C29/42 , G11C29/702
摘要： A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural network and a correct value is determined. The bits are respectively considered the at least one fault bit. A repair condition is determined based on the difference. The repair condition includes a correspondence between a position where the fault bit is located in the block and at least one non-fault bit in the memory. A value of at least one non-fault bit of the memory replaces a value of the fault bit based on the repair condition.
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公开(公告)号：US20240028245A1
公开(公告)日：2024-01-25
申请号：US17947170
申请日：2022-09-19
申请人： Skymizer Taiwan Inc.
发明人： Shu-Ming Liu , Kai-Chiang Wu , Wen Li Tang
IPC分类号： G06F3/06
CPC分类号： G06F3/0653 , G06F3/0619 , G06F3/0679
摘要： A memory apparatus and a data rearrangement method for computing in memory (CIM) are provided. The method includes determining whether first sequence data has two target bits that are both of a first value, inserting a non-target bit of a second value between the two target bits that are both of the first value and adjacent to each other to generate second sequence data, and receiving the second sequence data through memory cells in a memory to perform a multiply-accumulate (MAC) operation on the second sequence data. Each bit in the first sequence data is the first value or the second value. One of the two target bits is located adjacent to the other one of the two target bits in the first sequence data. The two target bits and the non-target bit are located in the first sequence data. Accordingly, the error rate is decreased.
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公开(公告)号：US11977432B2
公开(公告)日：2024-05-07
申请号：US17509064
申请日：2021-10-25
申请人： Skymizer Taiwan Inc.
发明人： Shu-Ming Liu , Jen-ho Kuo , Wen Li Tang , Kai-Chiang Wu
CPC分类号： G06F11/073 , G06F7/50 , G06F7/523 , G06F11/0763 , G06N3/04
摘要： A data processing circuit and a fault-mitigating method are provided. In the method, multiple sub-sequences are divided from sequence data. A first sub-sequence of the sub-sequences is accessed from a memory for a multiply-accumulate (MAC) operation to obtain a first computed result. The MAC operation is performed on a second sub-sequence of the sub-sequences in the memory to obtain a second computed result. The first and the second computed results are combined, where the combined result of the first and the second computed results is related to the result of the MAC operation on the sequence data directly. Accordingly, the error rate could be reduced, so as to mitigate fault.
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公开(公告)号：US11876527B2
公开(公告)日：2024-01-16
申请号：US17548575
申请日：2021-12-12
申请人： Skymizer Taiwan Inc.
发明人： Wen Li Tang , Shu-Ming Liu , Der-Yu Tsai , Po-Sheng Chang
CPC分类号： H03M1/1014 , G06F7/501 , G06F7/523 , G06N3/065 , H03M1/1071
摘要： An error calibration apparatus and method are provided. The method is adapted for calibrating a machine learning (ML) accelerator. The ML accelerator achieves computation by using an analog circuit. An error between an output value of one or more computing layers of a neural network and a corresponding corrected value is determined. The computation of the computing layers is achieved by the analog circuit. A calibration node is generated according to the error. The calibration node is located at the next layer of the computing layers. The calibration node is used to minimize the error. The calibration node is achieved by a digital circuit. Accordingly, error and distortion of the analog circuit could be reduced.
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公开(公告)号：US12045493B2
公开(公告)日：2024-07-23
申请号：US17947170
申请日：2022-09-19
申请人： Skymizer Taiwan Inc.
发明人： Shu-Ming Liu , Kai-Chiang Wu , Wen Li Tang
IPC分类号： G06F3/06
CPC分类号： G06F3/0653 , G06F3/0619 , G06F3/0679
摘要： A memory apparatus and a data rearrangement method for computing in memory (CIM) are provided. The method includes determining whether first sequence data has two target bits that are both of a first value, inserting a non-target bit of a second value between the two target bits that are both of the first value and adjacent to each other to generate second sequence data, and receiving the second sequence data through memory cells in a memory to perform a multiply-accumulate (MAC) operation on the second sequence data. Each bit in the first sequence data is the first value or the second value. One of the two target bits is located adjacent to the other one of the two target bits in the first sequence data. The two target bits and the non-target bit are located in the first sequence data. Accordingly, the error rate is decreased.
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公开(公告)号：US20240028452A1
公开(公告)日：2024-01-25
申请号：US18162601
申请日：2023-01-31
申请人： Skymizer Taiwan Inc.
发明人： Shu-Ming Liu , Kai-Chiang Wu , Wen Li Tang
IPC分类号： G06F11/10
CPC分类号： G06F11/104
摘要： A data processing circuit and a fault-mitigating method are provided. A first data is written into a memory. A computed result is determined according to one or more adjacent bits of the first data at faulty bits. According to the computed result, new values are determined. The new values replace the values of the first data at the faulty bits to form a second data. The first data includes multiple bits. The first data is image-related data, weights used by a multiply-accumulate (MAC) for extracting features of images, and/or values used by an activation calculation. The adjacent bits are adjacent to the faulty bits. The computed result is obtained through computing the values of the first data at non-faulty bits of the memory. Accordingly, an influence of a memory fault is reduced.
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公开(公告)号：US11461204B2
公开(公告)日：2022-10-04
申请号：US17213210
申请日：2021-03-25
申请人： Skymizer Taiwan Inc.
发明人： Shu-Ming Liu , Kai-Chiang Wu , Wen Li Tang
摘要： A data processing circuit and a fault-mitigating method, which are adapted for a memory having a faulty bit, are provided. The memory is configured to store data related to an image, a weight for a multiply-accumulate (MAC) operation of image feature extraction, and/or a value for an activation operation. Sequence data is written into the memory. The bit number of the sequence data equals to the bit number used for storing data in a sequence block of the memory. The sequence data is accessed from the memory, wherein the access of the faulty bit in the memory is ignored. The value of the faulty bit is replaced by the value of a non-faulty bit in the memory to form new sequence data. The new sequence data is used for MAC. Accordingly, the accuracy of image recognition can be improved for the faulty memory.
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公开(公告)号：US20230097158A1
公开(公告)日：2023-03-30
申请号：US17548575
申请日：2021-12-12
申请人： Skymizer Taiwan Inc.
发明人： Wen Li Tang , Shu-Ming Liu , Der-Yu Tsai , Po-Sheng Chang
摘要： An error calibration apparatus and method are provided. The method is adapted for calibrating a machine learning (ML) accelerator. The ML accelerator achieves computation by using an analog circuit. An error between an output value of one or more computing layers of a neural network and a corresponding corrected value is determined. The computation of the computing layers is achieved by the analog circuit. A calibration node is generated according to the error. The calibration node is located at the next layer of the computing layers. The calibration node is used to minimize the error. The calibration node is achieved by a digital circuit. Accordingly, error and distortion of the analog circuit could be reduced.
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公开(公告)号：US20230077991A1
公开(公告)日：2023-03-16
申请号：US17705415
申请日：2022-03-28
申请人： Skymizer Taiwan Inc.
发明人： Shu-Ming Liu , Kai-Chiang Wu , Chien-Fa Chen , Wen Li Tang
摘要： A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural network and a correct value is determined. The bits are respectively considered the at least one fault bit. A repair condition is determined based on the difference. The repair condition includes a correspondence between a position where the fault bit is located in the block and at least one non-fault bit in the memory. A value of at least one non-fault bit of the memory replaces a value of the fault bit based on the repair condition.
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公开(公告)号：US20220342736A1
公开(公告)日：2022-10-27
申请号：US17509064
申请日：2021-10-25
申请人： Skymizer Taiwan Inc.
发明人： Shu-Ming Liu , Jen-ho Kuo , Wen Li Tang , Kai-Chiang Wu
摘要： A data processing circuit and a fault-mitigating method are provided. In the method, multiple sub-sequences are divided from sequence data. A first sub-sequence of the sub-sequences is accessed from a memory for a multiply-accumulate (MAC) operation to obtain a first computed result. The MAC operation is performed on a second sub-sequence of the sub-sequences in the memory to obtain a second computed result. The first and the second computed results are combined, where the combined result of the first and the second computed results is related to the result of the MAC operation on the sequence data directly. Accordingly, the error rate could be reduced, so as to mitigate fault.
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