公开(公告)号：US07795933B2

公开(公告)日：2010-09-14

申请号：US12253551

申请日：2008-10-17

申请人： Ming-Shih Yu ,  Song-Rong Han

发明人： Ming-Shih Yu ,  Song-Rong Han

IPC分类号： H03L7/06

CPC分类号： H03L7/18 ,  H03L7/099

摘要： A timing-signal generator includes a PLL circuit, one or more rising/falling edge generating unit and one or more timing-signal generating unit. In response to a reference signal with a frequency Fref, the PLL outputs M voltage controlled signals with the same frequency Fvco=N*Fref and equally distributed phase differences. The rising/falling edge generating unit is for generating a rising point signal and a falling point signal corresponding to respective ones one of M*P candidate timing points which are defined in a cycle of the reference signal according to the M voltage controlled signals. The timing-signal generating unit coupled to the rising/falling edge generating unit is for generating a timing signal which toggles high in response to the rising point signal and toggles low in response to the falling point signal.

摘要翻译： 定时信号发生器包括PLL电路，一个或多个上升/下降沿产生单元和一个或多个定时信号产生单元。 响应于具有频率Fref的参考信号，PLL输出具有相同频率的M个电压控制信号Fvco = N * Fref和相等分布的相位差。 上升/下降沿产生单元用于产生对应于根据M个电压控制信号在参考信号的周期中定义的M * P候选定时点中的相应一个的上升点信号和下降点信号。 耦合到上升/下降沿产生单元的定时信号产生单元用于产生响应于上升点信号而切换高电平的定时信号，并响应于下降点信号而切换低电平。

公开(公告)号：US07755398B2

公开(公告)日：2010-07-13

申请号：US11871161

申请日：2007-10-12

申请人： Song-Rong Han ,  Ming-Shih Yu

发明人： Song-Rong Han ,  Ming-Shih Yu

IPC分类号： H03K5/153

CPC分类号： H03K5/135 ,  H03H2210/021 ,  H03H2210/043 ,  H03K2005/00097

摘要： A time constant calibration device includes: a first voltage generating circuit utilizing a first current passing through a capacitive component to generate a first voltage; a second voltage generating circuit utilizing a second current passing through a resistive component to generate a second voltage; and a comparing circuit for comparing the first voltage with the second voltage to generate a comparing signal, wherein the first voltage generating circuit comprises an analog adjusting component for adjusting the first voltage according to the comparing signal until the first voltage is equal to the second voltage, whereby an RC time constant defined by an equivalent capacitance corresponding to the first current passing through the capacitive component and an equivalent impedance corresponding to the second current passing through the resistive component reaches a predetermined value.

摘要翻译： 时间常数校准装置包括：第一电压产生电路，利用通过电容分量的第一电流产生第一电压; 利用通过电阻元件产生第二电压的第二电流的第二电压产生电路; 以及比较电路，用于比较第一电压与第二电压以产生比较信号，其中第一电压产生电路包括用于根据比较信号调整第一电压的模拟调整组件，直到第一电压等于第二电压 由此由对应于通过电容分量的第一电流的等效电容和对应于通过电阻分量的第二电流的等效阻抗定义的RC时间常数达到预定值。

公开(公告)号：US20080129402A1

公开(公告)日：2008-06-05

申请号：US11533038

申请日：2006-09-19

申请人： Song-Rong Han ,  Ming-Shih Yu

发明人： Song-Rong Han ,  Ming-Shih Yu

IPC分类号： H03B5/12

CPC分类号： H03L7/099 ,  H03L7/095 ,  H03L7/1075 ,  H03L7/18 ,  Y10S331/02

摘要： An automatic switching phase-locked loop (PLL) is disclosed, including a phase detector, a charge pump generating a pump current, a band selector receiving a control voltage to produce a band selection signal and a voltage setting signal based the control voltage, a loop filter generating the control voltage corresponding to the pump current and setting the control voltage based on the voltage setting signal, and a multi-band voltage control oscillator (VCO) coupled to the control voltage and the band selection signal, selecting one of a plurality of operating bands based on the band selection signal, and providing an output signal of a frequency within the selected operating band based on the control voltage.

摘要翻译： 公开了一种自动切换锁相环（PLL），包括相位检测器，产生泵浦电流的电荷泵，接收控制电压以产生频带选择信号的频带选择器和基于控制电压的电压设置信号， 产生对应于泵浦电流的控制电压并基于电压设置信号设置控制电压，以及耦合到控制电压和频带选择信号的多频带压控振荡器（VCO），选择多个 基于所述频带选择信号的工作频带，以及基于所述控制电压提供所选择的工作频带内的频率的输出信号。

公开(公告)号：US20160087636A1

公开(公告)日：2016-03-24

申请号：US14527779

申请日：2014-10-30

申请人： Chia-Liang Lai ,  Song-Rong Han ,  Jung-Yu Chang ,  Wei-Ming Lin

发明人： Chia-Liang Lai ,  Song-Rong Han ,  Jung-Yu Chang ,  Wei-Ming Lin

IPC分类号： H03K21/02

CPC分类号： H03L7/1976 ,  H03K21/023 ,  H03K23/68 ,  H03L7/1974

摘要： A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.

摘要翻译： 提供时钟发生装置及其分数分频器。 分数分频器包括分频器（FD），多个采样器，选择器和控制电路。 FD的输入端耦合到多相频率发生电路的输出端。 采样器的输入端耦合到FD的输出端。 采样器的触发端接收采样时钟信号。 选择器的输入端耦合到采样器的输出端。 选择器的输出端耦合到多相频率发生电路的反馈端。 控制电路向选择器的控制端提供分数代码，以便控制选择器选择性地将一个采样器的输出端耦合到多相频率发生电路的反馈端。

公开(公告)号：US20110006817A1

公开(公告)日：2011-01-13

申请号：US12499781

申请日：2009-07-08

申请人： Song-Rong Han ,  Kuo-Hsiung Wu ,  Chia-Liang Lai

发明人： Song-Rong Han ,  Kuo-Hsiung Wu ,  Chia-Liang Lai

IPC分类号： H03K4/06

CPC分类号： H03K4/06 ,  G06F1/08 ,  H03K3/84

摘要： A triangular wave generator, comprising: a first frequency divider, for utilizing a first positive integer to divide a first frequency of a first periodical signal to generate a first frequency-divided signal; a second frequency divider, for utilizing a second positive integer to divide a second frequency, which equals the first frequency multiplying a third positive integer, of a second periodical signal to generate a second frequency-divided signal; and an up/down counter, for generating a triangular wave first and second frequency-divided frequencies respectively belonging to first and second frequency divided signals; wherein a frequency of the triangular wave equals to the first frequency-divided frequency, and an amplitude of the triangular wave is determined according to a ratio of the first and second frequency-divided frequencies.

摘要翻译： 一种三角波发生器，包括：第一分频器，用于利用第一正整数来分频第一周期信号的第一频率以产生第一分频信号; 第二分频器，用于利用第二正整数来分频第二周期信号的等于第三正整数的第一频率的第二频率以产生第二分频信号; 以及用于产生分别属于第一和第二分频信号的三角波第一和第二分频频率的向上/向下计数器; 其中所述三角波的频率等于所述第一分频频率，并且根据所述第一和第二分频频率的比率来确定所述三角波的振幅。

公开(公告)号：US20100086009A1

公开(公告)日：2010-04-08

申请号：US12246953

申请日：2008-10-07

申请人： Song-Rong Han

发明人： Song-Rong Han

IPC分类号： H04B1/69

CPC分类号： H03K3/84 ,  H04B1/69

摘要： A spread-spectrum clock generator (SSCG) and a spread-spectrum clock generating method are provided. The SSCG includes a first spread-spectrum module, a second spread-spectrum module, and a waveform module. The first spread-spectrum module generates a first spread-spectrum clock signal by modulating the frequency of a first input clock signal with a parallel delay configuration. The second spread-spectrum module generates a second spread-spectrum clock signal by modulating the frequency of a second input clock signal with the same parallel delay configuration. The waveform module is coupled to the first spread-spectrum module and the second spread-spectrum module for generating an output spread-spectrum clock signal according to the first and the second spread-spectrum clock signals.

摘要翻译： 提供了扩频时钟发生器（SSCG）和扩频时钟产生方法。 SSCG包括第一扩频模块，第二扩频模块和波形模块。 第一扩频模块通过以并行延迟配置调制第一输入时钟信号的频率来产生第一扩频时钟信号。 第二扩频模块通过以相同的并行延迟配置调制第二输入时钟信号的频率来产生第二扩频时钟信号。 波形模块耦合到第一扩频模块和第二扩频模块，用于根据第一和第二扩频时钟信号产生输出扩频时钟信号。

公开(公告)号：US20060284656A1

公开(公告)日：2006-12-21

申请号：US11160292

申请日：2005-06-17

申请人： Ming-Shih Yu ,  Song-Rong Han

发明人： Ming-Shih Yu ,  Song-Rong Han

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/095

摘要： The present invention discloses a delay-locked loop device capable of anti-false-locking, which comprises: a voltage control delay circuit comprising a plurality of delay units in a series for generating a delayed phase according to a reference phase and a control voltage; a phase detector coupled to the voltage control delay circuit for generating a control signal according to a lock indication signal, the reference phase, and the delayed phase; a charge pump coupled to the phase detector for transmitting the control voltage to the voltage control delay circuit according to the control signal; and a lock detector coupled to the voltage control delay circuit for generating the lock indication signal for the phase detector according to output phases of at least one delay unit of the voltage control delay circuit.

摘要翻译： 本发明公开了一种能够进行防伪锁的延迟锁定环路装置，包括：电压控制延迟电路，包括多个串联延迟单元，用于根据参考相位和控制电压产生延迟相位; 耦合到电压控制延迟电路的相位检测器，用于根据锁定指示信号，参考相位和延迟相位产生控制信号; 电荷泵，耦合到所述相位检测器，用于根据所述控制信号将所述控制电压发送到所述电压控制延迟电路; 以及耦合到电压控制延迟电路的锁定检测器，用于根据电压控制延迟电路的至少一个延迟单元的输出相位产生用于相位检测器的锁定指示信号。

公开(公告)号：US20090128203A1

公开(公告)日：2009-05-21

申请号：US12253551

申请日：2008-10-17

申请人： MING-SHIH YU ,  SONG-RONG HAN

发明人： MING-SHIH YU ,  SONG-RONG HAN

IPC分类号： H03L7/06

CPC分类号： H03L7/18 ,  H03L7/099

摘要： A timing-signal generator includes a PLL circuit, one or more rising/falling edge generating unit and one or more timing-signal generating unit. In response to a reference signal with a frequency Fref, the PLL outputs M voltage controlled signals with the same frequency Fvco=N*Fref and equally distributed phase differences. The rising/falling edge generating unit is for generating a rising point signal and a falling point signal corresponding to respective ones one of M*P candidate timing points which are defined in a cycle of the reference signal according to the M voltage controlled signals. The timing-signal generating unit coupled to the rising/falling edge generating unit is for generating a timing signal which toggles high in response to the rising point signal and toggles low in response to the falling point signal.

摘要翻译： 定时信号发生器包括PLL电路，一个或多个上升/下降沿产生单元和一个或多个定时信号产生单元。 响应于具有频率Fref的参考信号，PLL输出具有相同频率的M个电压控制信号Fvco = N * Fref和相等分布的相位差。 上升/下降沿产生单元用于产生对应于根据M个电压控制信号在参考信号的周期中定义的M * P候选定时点中的相应一个的上升点信号和下降点信号。 耦合到上升/下降沿产生单元的定时信号产生单元用于产生响应于上升点信号而切换高电平的定时信号，并响应于下降点信号而切换低电平。

公开(公告)号：US07656214B1

公开(公告)日：2010-02-02

申请号：US12273245

申请日：2008-11-18

申请人： Song-Rong Han

发明人： Song-Rong Han

IPC分类号： H03K3/00

CPC分类号： H03K3/84 ,  H03K7/06 ,  H04B15/02 ,  H04B2215/067

摘要： A spread-spectrum clock generator is provided, which includes a modulation module and a voltage-controlled delay line (VCDL). The modulation module provides a control voltage. The VCDL is coupled to the modulation module and is configured for modulating the frequency of an input clock signal according to the control voltage, so as to output an output clock signal. The modulation profile of the output clock signal is a periodic function of time.

摘要翻译： 提供了扩频时钟发生器，其包括调制模块和电压控制延迟线（VCDL）。 调制模块提供控制电压。 VCDL耦合到调制模块，并被配置为根据控制电压调制输入时钟信号的频率，以输出输出时钟信号。 输出时钟信号的调制曲线是时间的周期函数。

公开(公告)号：US07471158B2

公开(公告)日：2008-12-30

申请号：US11533038

申请日：2006-09-19

申请人： Song-Rong Han ,  Ming-Shih Yu

发明人： Song-Rong Han ,  Ming-Shih Yu

IPC分类号： H03L7/095 ,  H03L7/099

CPC分类号： H03L7/099 ,  H03L7/095 ,  H03L7/1075 ,  H03L7/18 ,  Y10S331/02

摘要： An automatic switching phase-locked loop (PLL) is disclosed, including a phase detector, a charge pump generating a pump current, a band selector receiving a control voltage to produce a band selection signal and a voltage setting signal based the control voltage, a loop filter generating the control voltage corresponding to the pump current and setting the control voltage based on the voltage setting signal, and a multi-band voltage control oscillator (VCO) coupled to the control voltage and the band selection signal, selecting one of a plurality of operating bands based on the band selection signal, and providing an output signal of a frequency within the selected operating band based on the control voltage.

摘要翻译： 公开了一种自动切换锁相环（PLL），包括相位检测器，产生泵浦电流的电荷泵，接收控制电压以产生频带选择信号的频带选择器和基于控制电压的电压设置信号， 产生对应于泵浦电流的控制电压并基于电压设置信号设置控制电压，以及耦合到控制电压和频带选择信号的多频带压控振荡器（VCO），选择多个 基于所述频带选择信号的工作频带，以及基于所述控制电压提供所选择的工作频带内的频率的输出信号。