公开(公告)号：US5440714A

公开(公告)日：1995-08-08

申请号：US990641

申请日：1992-12-14

申请人： Song-Tine Wang

发明人： Song-Tine Wang

IPC分类号： G06F9/34 ,  G06F9/30 ,  G06F9/42

CPC分类号： G06F9/30127 ,  G06F9/30145

摘要： The present invention comprises a decoding system for decoding a data accessing instruction for accessing data stored in a plurality of registers wherein the registers are of different types including a global type, a local type, an input type and an output type, the registers being cataloged into a plurality of windows arranged in a predefined window sequence wherein each window including a plurality of registers of each of the types arranged in a predefined register sequence wherein the output registers of one of the windows being overlapping with the input registers of an adjacent window which being next in sequence of the window sequence. The decoding system comprises an instruction issuing means for issuing a data accessing instruction including a plurality of bits wherein the bits being encoded in an order corresponding to the window sequence and the register sequence and a set of bits of the instruction is used for defining a corresponding window and a corresponding type of the registers. The decoding system further comprises a decoding means for decoding each sets of bits of the instruction utilizing the overlapping of input registers with output registers between two adjacent register windows to select a register in one of windows for retrieving the stored data therefrom.

摘要翻译： 本发明包括一个解码系统，用于对存储在多个寄存器中的数据进行访问的数据访问指令进行解码，其中寄存器是不同类型的，包括全局类型，本地类型，输入类型和输出类型，被编目的寄存器 以预定窗口顺序布置的多个窗口，其中每个窗口包括布置在预定义寄存器序列中的每种类型的多个寄存器，其中一个窗口的输出寄存器与相邻窗口的输入寄存器重叠， 接下来是窗口序列的顺序。 解码系统包括指令发布装置，用于发出包括多个比特的数据访问指令，其中以与窗口序列和寄存器序列相对应的顺序编码比特，并且使用该指令的一组位来定义对应的 窗口和相应类型的寄存器。 解码系统还包括解码装置，用于利用输入寄存器与两个相邻寄存器窗口之间的输出寄存器的重叠来解码指令的每一组，以在其中一个窗口中选择用于从其中检索存储的数据的寄存器。

公开(公告)号：US5619155A

公开(公告)日：1997-04-08

申请号：US460225

申请日：1995-06-02

申请人： Song-Tine Wang

发明人： Song-Tine Wang

IPC分类号： G06F1/04 ,  H01L21/822 ,  H01L27/04 ,  H03K5/26 ,  H03K19/003 ,  H03K17/20 ,  H03K7/00

CPC分类号： H03K5/26 ,  H03K19/003

摘要： An IC chip operation inhibitor to prevent operation of an IC chip in a system having a clock rate that exceeds a predetermined reference clock rate for the chip. The inhibitor has a frequency detecting device that generates at least one reference frequency. It compares the system clock with the reference frequency and prevents the chip from operating if the system clock frequency is greater than the reference frequency. The invention includes an external actuating device coupled to the frequency detecting device for generating a compare enable signal to actuate the comparing function of the frequency detecting device, and for generating a frequency select signal for selecting one of the built-in reference frequencies to be compared with the system oscillating frequency. The external actuating device may be turned off in order not to actuate the comparing function of the frequency detecting device when it is sure that the system oscillating frequency will not be higher than the reference frequency.

摘要翻译： 一种IC芯片操作抑制器，用于防止具有超过芯片的预定参考时钟频率的时钟速率的系统中的IC芯片的操作。 抑制剂具有产生至少一个参考频率的频率检测装置。 它将系统时钟与参考频率进行比较，如果系统时钟频率大于参考频率，则可以防止芯片工作。 本发明包括耦合到频率检测装置的外部致动装置，用于产生用于激励频率检测装置的比较功能的比较使能信号，并且用于产生用于选择要比较的内置参考频率之一的频率选择信号 与系统振荡频率。 当确定系统振荡频率不会高于参考频率时，可以关闭外部致动装置，以便不致动频率检测装置的比较功能。

公开(公告)号：US5844825A

公开(公告)日：1998-12-01

申请号：US707222

申请日：1996-09-03

申请人： Song-Tine Wang ,  Shih-Yin Lin ,  Shing-Wu Tung

发明人： Song-Tine Wang ,  Shih-Yin Lin ,  Shing-Wu Tung

IPC分类号： G06F5/01 ,  G06F7/76 ,  G11C19/00 ,  G11C19/28

CPC分类号： G11C19/00 ,  G06F5/01 ,  G11C19/28 ,  G06F7/768

摘要： A bidirectional shifter circuit is disclosed for shifting an inputted data word a chosen number of bit positions in either a first or a second chosen direction. The bidirectional shifter circuit is provided with a first bit-reversing circuit which receives an inputted data word. In response to choosing a first shift direction, the first bit-reversing circuit outputs the data word with the bits in their original order. In response to choosing the second shift direction, the first bit-reversing circuit outputs the data word with the bits in reverse order. A single-direction shifter circuit is provided which receives the data word outputted by the first bit-reversing circuit and shifts the received data word the chosen number of bit positions in the first direction. A second bit-reversing circuit is provided which receives the shifted data word and which, in response to choosing the first shift direction, outputs the data word with the bits in the same order as received and, in response to choosing the second shift direction, outputs the data word with the bits in reverse order.

摘要翻译： 公开了一种双向移位器电路，用于将输入的数据字在选择的第一或第二选择方向上移位所选择的位数位置。 双向移位器电路设置有接收输入数据字的第一位反转电路。 响应于选择第一移位方向，第一位反转电路以其原始顺序输出具有位的数据字。 响应于选择第二移位方向，第一位反转电路以相反的顺序输出具有位的数据字。 提供单向移位器电路，其接收由第一位反转电路输出的数据字，并将接收到的数据字在第一方向上移位所选择的位数位置。 提供了第二位反转电路，其接收移位的数据字，并且响应于选择第一移位方向，以与接收的相同次序输出数据字，并且响应于选择第二移位方向， 以相反的顺序输出数据字。