公开(公告)号：US5844825A

公开(公告)日：1998-12-01

申请号：US707222

申请日：1996-09-03

申请人： Song-Tine Wang ,  Shih-Yin Lin ,  Shing-Wu Tung

发明人： Song-Tine Wang ,  Shih-Yin Lin ,  Shing-Wu Tung

IPC分类号： G06F5/01 ,  G06F7/76 ,  G11C19/00 ,  G11C19/28

CPC分类号： G11C19/00 ,  G06F5/01 ,  G11C19/28 ,  G06F7/768

摘要： A bidirectional shifter circuit is disclosed for shifting an inputted data word a chosen number of bit positions in either a first or a second chosen direction. The bidirectional shifter circuit is provided with a first bit-reversing circuit which receives an inputted data word. In response to choosing a first shift direction, the first bit-reversing circuit outputs the data word with the bits in their original order. In response to choosing the second shift direction, the first bit-reversing circuit outputs the data word with the bits in reverse order. A single-direction shifter circuit is provided which receives the data word outputted by the first bit-reversing circuit and shifts the received data word the chosen number of bit positions in the first direction. A second bit-reversing circuit is provided which receives the shifted data word and which, in response to choosing the first shift direction, outputs the data word with the bits in the same order as received and, in response to choosing the second shift direction, outputs the data word with the bits in reverse order.

摘要翻译： 公开了一种双向移位器电路，用于将输入的数据字在选择的第一或第二选择方向上移位所选择的位数位置。 双向移位器电路设置有接收输入数据字的第一位反转电路。 响应于选择第一移位方向，第一位反转电路以其原始顺序输出具有位的数据字。 响应于选择第二移位方向，第一位反转电路以相反的顺序输出具有位的数据字。 提供单向移位器电路，其接收由第一位反转电路输出的数据字，并将接收到的数据字在第一方向上移位所选择的位数位置。 提供了第二位反转电路，其接收移位的数据字，并且响应于选择第一移位方向，以与接收的相同次序输出数据字，并且响应于选择第二移位方向， 以相反的顺序输出数据字。

公开(公告)号：US20120151192A1

公开(公告)日：2012-06-14

申请号：US13112307

申请日：2011-05-20

申请人： Hsien-Ching Hsieh ,  Po-Han Huang ,  Shing-Wu Tung

发明人： Hsien-Ching Hsieh ,  Po-Han Huang ,  Shing-Wu Tung

IPC分类号： G06F1/32 ,  G06F9/30

CPC分类号： G06F9/38 ,  G06F1/3237 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30076 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3885 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D10/172

摘要： A very long instruction word (VLIW) processor and an apparatus with power management and a method of power management therefor are provided in consistent with the exemplary embodiments of the disclosure. The power management method includes the following steps. Valid instruction(s) and no operation (NOP) instruction(s) of an input instruction package are rearranged to output a transcoded instruction package, wherein the transcoded instruction package by the rearrangement has its NOP instruction(s) corresponding to at least one execution unit, which is to be placed in power reduction state, of a VLIW processor. Power reduction control is selectively performed on at least one execution unit corresponding to at least one NOP instruction of the transcoded instruction package according to the transcoded instruction package.

摘要翻译： 根据本公开的示例性实施例，提供了一种非常长的指令字（VLIW）处理器和具有功率管理的装置及其电源管理方法。 电源管理方法包括以下步骤。 重新排列输入指令包的有效指令和无操作（NOP）指令以输出代码转换的指令包，其中通过重新排列的经转码的指令包具有与至少一个执行对应的NOP指令 VLIW处理器将被放置在功率降低状态的单元。 根据代码转换的指令包，对与代码转换的指令包的至少一个NOP指令相对应的至少一个执行单元有选择地执行功率降低控制。

公开(公告)号：US07441165B2

公开(公告)日：2008-10-21

申请号：US11164586

申请日：2005-11-29

申请人： Tsai-Wang Tseng ,  Shih-Chia Kao ,  Shing-Wu Tung

发明人： Tsai-Wang Tseng ,  Shih-Chia Kao ,  Shing-Wu Tung

IPC分类号： G11C29/00

CPC分类号： G11C29/40 ,  G11C17/14 ,  G11C2029/0405

摘要： A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a plurality of memory cells of the ROM according to verification data stored in a verification area of the memory cells of the ROM.

摘要翻译： 公开了一种用于控制ROM的操作的只读存储器（ROM）和相关方法。 ROM的内置自检（BIST）电路根据存储在ROM的存储单元的验证区域中的验证数据来验证存储在ROM的多个存储单元的系统区域中的系统数据。

公开(公告)号：US20060206771A1

公开(公告)日：2006-09-14

申请号：US11164586

申请日：2005-11-29

申请人： Tsai-Wang Tseng ,  Shih-Chia Kao ,  Shing-Wu Tung

发明人： Tsai-Wang Tseng ,  Shih-Chia Kao ,  Shing-Wu Tung

IPC分类号： G01R31/28

CPC分类号： G11C29/40 ,  G11C17/14 ,  G11C2029/0405

摘要： A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a plurality of memory cells of the ROM according to verification data stored in a verification area of the memory cells of the ROM.

摘要翻译： 公开了一种用于控制ROM的操作的只读存储器（ROM）和相关方法。 ROM的内置自检（BIST）电路根据存储在ROM的存储单元的验证区域中的验证数据来验证存储在ROM的多个存储单元的系统区域中的系统数据。

公开(公告)号：US08645116B2

公开(公告)日：2014-02-04

申请号：US13107444

申请日：2011-05-13

申请人： Chi-Hung Lin ,  Che-Yu Liao ,  Ching-Hsiang Chuang ,  Shing-Wu Tung

发明人： Chi-Hung Lin ,  Che-Yu Liao ,  Ching-Hsiang Chuang ,  Shing-Wu Tung

IPC分类号： G06F17/50

CPC分类号： G06F11/3636 ,  G06F11/3664 ,  G06F11/3696

摘要： A hybrid simulation model includes a real model, a bus interface and an acceleration model. The real model simulates a group of instructions. The acceleration model includes a trace generation unit, a trace replay unit, a selection unit, a snapshot generation and load unit and a virtual breakpoint control unit. The trace generation unit records at least one trace file of the real model in a first simulation. The trace replay unit reads and accordingly accesses the at least one trace file. The selection unit dynamically switches to perform a real simulation or a trace simulation. The snapshot generation and load unit generates at least one status snapshot file and loads the at least one status snapshot file to the real model in repeated simulations. The virtual breakpoint control unit controls the selection unit to switch between the trace simulation and the real simulation according to a virtual breakpoint.

摘要翻译： 混合模拟模型包括实际模型，总线接口和加速模型。 真正的模型模拟了一组指令。 加速度模型包括跟踪生成单元，跟踪重放单元，选择单元，快照生成和加载单元以及虚拟断点控制单元。 跟踪生成单元在第一模拟中记录真实模型的至少一个跟踪文件。 跟踪重放单元读取并相应地访问至少一个跟踪文件。 选择单元动态地切换以执行真实的模拟或跟踪模拟。 快照生成和加载单元生成至少一个状态快照文件，并在重复模拟中将至少一个状态快照文件加载到真实模型。 虚拟断点控制单元控制选择单元根据虚拟断点在跟踪仿真和真实仿真之间切换。

公开(公告)号：US20120179447A1

公开(公告)日：2012-07-12

申请号：US13107444

申请日：2011-05-13

申请人： Chi-Hung Lin ,  Che-Yu Liao ,  Ching-Hsiang Chuang ,  Shing-Wu Tung

发明人： Chi-Hung Lin ,  Che-Yu Liao ,  Ching-Hsiang Chuang ,  Shing-Wu Tung

IPC分类号： G06F9/45

CPC分类号： G06F11/3636 ,  G06F11/3664 ,  G06F11/3696

摘要： A hybrid simulation model includes a real model, a bus interface and an acceleration model. The real model simulates a group of instructions. The acceleration model includes a trace generation unit, a trace replay unit, a selection unit, a snapshot generation and load unit and a virtual breakpoint control unit. The trace generation unit records at least one trace file of the real model in a first simulation. The trace replay unit reads and accordingly accesses the at least one trace file. The selection unit dynamically switches to perform a real simulation or a trace simulation. The snapshot generation and load unit generates at least one status snapshot file and loads the at least one status snapshot file to the real model in repeated simulations. The virtual breakpoint control unit controls the selection unit to switch between the trace simulation and the real simulation according to a virtual breakpoint.

摘要翻译： 混合模拟模型包括实际模型，总线接口和加速模型。 真正的模型模拟了一组指令。 加速度模型包括跟踪生成单元，跟踪重放单元，选择单元，快照生成和加载单元以及虚拟断点控制单元。 跟踪生成单元在第一模拟中记录真实模型的至少一个跟踪文件。 跟踪重放单元读取并相应地访问至少一个跟踪文件。 选择单元动态地切换以执行真实的模拟或跟踪模拟。 快照生成和加载单元生成至少一个状态快照文件，并在重复模拟中将至少一个状态快照文件加载到真实模型。 虚拟断点控制单元控制选择单元根据虚拟断点在跟踪仿真和真实仿真之间切换。

公开(公告)号：US06675337B1

公开(公告)日：2004-01-06

申请号：US09630905

申请日：2000-08-02

申请人： Shing-Wu Tung ,  Chun-Yao Wang ,  Jing-Yang Jou

发明人： Shing-Wu Tung ,  Chun-Yao Wang ,  Jing-Yang Jou

IPC分类号： G01R3128

CPC分类号： G01R31/318342

摘要： A built-in verification circuit having a circuit-under-test circuit, a test pattern generator, a bi-directional signal flow switch and three unidirectional, signal flow switches. The test pattern generator produces a testing pattern based on an input/output port order fault model. The bi-directional signal flow switch is positioned between the input terminal of the built-in verification circuit and the circuit-under-test circuit. The first unidirectional signal flow switch is positioned between the circuit-under-test circuit and the test pattern generator. The second unidirectional signal flow switch is positioned between the circuit-under-test circuit and the output terminal of the built-in verification circuit. The third unidirectional signal flow switch is positioned between the test pattern generator and the output terminal of the built-in verification circuit. The bi-directional signal flow switch and the first unidirectional signal flow switch are used for controlling the input terminal of the built-in verification circuit and the signal flow direction of the test pattern generator. The second and the third unidirectional signal flow switch are used for controlling the signal source of the output from the built-in verification circuit.

摘要翻译： 具有电路不足测试电路，测试图形发生器，双向信号流开关和三个单向信号流开关的内置验证电路。 测试模式生成器基于输入/输出端口顺序故障模型生成测试模式。 双向信号流开关位于内置验证电路的输入端和被测电路之间。 第一单向信号流开关位于测试电路和测试图案发生器之间。 第二单向信号流开关位于被测电路和内置验证电路的输出端之间。 第三单向信号流开关位于测试图形发生器和内置验证电路的输出端之间。 双向信号流开关和第一单向信号流开关用于控制内置验证电路的输入端和测试模式发生器的信号流向。 第二和第三单向信号流开关用于控制来自内置验证电路的输出的信号源。

公开(公告)号：US08769245B2

公开(公告)日：2014-07-01

申请号：US13112307

申请日：2011-05-20

申请人： Hsien-Ching Hsieh ,  Po-Han Huang ,  Shing-Wu Tung

发明人： Hsien-Ching Hsieh ,  Po-Han Huang ,  Shing-Wu Tung

IPC分类号： G06F9/38 ,  G06F1/32 ,  G06F9/30

CPC分类号： G06F9/38 ,  G06F1/3237 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30076 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3885 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D10/172

摘要： A very long instruction word (VLIW) processor and an apparatus with power management and a method of power management therefor are provided in consistent with the exemplary embodiments of the disclosure. The power management method includes the following steps. Valid instruction(s) and no operation (NOP) instruction(s) of an input instruction package are rearranged to output a transcoded instruction package, wherein the transcoded instruction package by the rearrangement has its NOP instruction(s) corresponding to at least one execution unit, which is to be placed in power reduction state, of a VLIW processor. Power reduction control is selectively performed on at least one execution unit corresponding to at least one NOP instruction of the transcoded instruction package according to the transcoded instruction package.

摘要翻译： 根据本公开的示例性实施例，提供了一种非常长的指令字（VLIW）处理器和具有功率管理的装置及其电源管理方法。 电源管理方法包括以下步骤。 重新排列输入指令包的有效指令和无操作（NOP）指令以输出代码转换的指令包，其中通过重新排列的经转码的指令包具有与至少一个执行对应的NOP指令 VLIW处理器将被放置在功率降低状态的单元。 根据代码转换的指令包，对与代码转换的指令包的至少一个NOP指令相对应的至少一个执行单元有选择地执行功率降低控制。

公开(公告)号：US5995991A

公开(公告)日：1999-11-30

申请号：US677551

申请日：1996-07-18

申请人： Biing-Huang Huang ,  Shing-Wu Tung

发明人： Biing-Huang Huang ,  Shing-Wu Tung

IPC分类号： G06F7/57 ,  G06F7/38

CPC分类号： G06F7/483 ,  G06F2207/3808

摘要： A method for representing arithmetic values on which arithmetic operations can be performed uses operands having a fixed number of bits. In a first step, a plurality of operands are stored in a memory, wherein each operand has a bit pattern representing a particular value. In a second step, a tag associated with each of the operands is also stored in the same or a different memory. Each of the tags has a tag value that indicates whether or not its associated operand represents an ordinary operand value or a special operand value. If the operand represents a special operand value, the tag value also indicates which of a predefined set of special operand values is represented by the associated operand. A result of an arithmetic operation can be generated by, in a first step, inputting at least a first operand and a first tag to an arithmetic section. In a second step, the arithmetic section determines a value of the result of the arithmetic operation based on the special operand indicated by the first tag and independently of a value of the first operand. A tag associated with a result of an arithmetic calculation can be generated by, in a first step, generating in an arithmetic section a result of an arithmetic operation on at least one operand. If the generation of the result produces one of a predetermined set of special operands, a tag generator generates a tag having a predetermined tag value corresponding to the produced special operand. Illustratively the tag generator alternatively generates a predetermined tag value indicating that the result is not a special operand if the result is not a special operand.

摘要翻译： 用于表示可以执行算术运算的算术值的方法使用具有固定位数的操作数。 在第一步骤中，多个操作数存储在存储器中，其中每个操作数具有表示特定值的位模式。 在第二步骤中，与每个操作数相关联的标签也存储在相同或不同的存储器中。 每个标签都有一个标签值，表示其关联的操作数是否代表一个普通的操作数值或一个特殊的操作数值。 如果操作数表示一个特殊的操作数值，那么标签值还指出了一组预定义的特殊操作数值中的哪一个由相关的操作数表示。 可以通过在第一步骤中至少将第一操作数和第一标签输入到运算部来产生算术运算的结果。 在第二步骤中，运算部根据由第一标签指定的特殊操作数，独立于第一操作数的值，确定算术运算结果的值。 可以通过在第一步骤中在运算部分中生成对至少一个操作数进行算术运算的结果来生成与运算结果相关联的标签。 如果结果的产生产生预定的一组特殊操作数之一，则标签发生器产生具有与所产生的特殊操作数对应的预定标签值的标签。 示例性地，如果结果不是特殊操作数，则标签发生器交替地产生指示结果不是特殊操作数的预定标签值。