公开(公告)号：US06859051B1

公开(公告)日：2005-02-22

申请号：US10452373

申请日：2003-06-02

Applicant: Spiro Poulis ,  John Evans ,  Shayne Messerly

Inventor： Spiro Poulis ,  John Evans ,  Shayne Messerly

IPC: H04B1/58 ,  G01R27/08 ,  H03L5/00 ,  H04M1/24

CPC classification number: H04B1/58

Abstract: The present invention synthesizes a prescribed impedance. The impedance is synthesized by generating a current having a value substantially equal to a voltage divided by a prescribed impedance. Sensing the line voltage and converting that sensed line voltage to its digital equivalent accomplish this first step. The digital line voltage is processed by a factor related to the prescribed impedance to produce an output voltage that has a value substantially equal to the sensed voltage divided by the prescribed impedance. The output voltage controls a voltage to current converter that generates the appropriate current across the points or terminals where the line voltage was measured. Thus, the prescribed impedance is generated across these points or terminals because the line voltage divided by the generated current is substantially equal to the prescribed impedance.

Abstract translation: 本发明合成规定的阻抗。 通过产生具有基本上等于被规定阻抗除以的电压的值的电流来合成阻抗。 感测线路电压并将感测到的线路电压转换为其数字等效电压完成了第一步。 数字线路电压由与规定阻抗相关的因子处理，以产生具有基本上等于感测电压除以规定阻抗的值的输出电压。 输出电压控制电压到电流转换器，其在测量线路电压的点或端子处产生适当的电流。 因此，由于产生的电流除以的线电压基本上等于规定的阻抗，所以在这些点或端子之间产生规定的阻抗。

公开(公告)号：US06434161B1

公开(公告)日：2002-08-13

申请号：US09030077

申请日：1998-02-25

Applicant: Brent C. Higbee ,  Gerald A. Wilson ,  Garn H. Morrell ,  Spiro Poulis

Inventor： Brent C. Higbee ,  Gerald A. Wilson ,  Garn H. Morrell ,  Spiro Poulis

IPC: H04L1256

CPC classification number: H04L49/901 ,  G06F13/105 ,  G06F13/32 ,  G06F13/385 ,  H04L49/90

Abstract: An apparatus and method for transferring data between a host system and a communication network via a communication module wherein the communication module presents a UART-like interface to the host system. The communication module is comprised of an emulated UART module, a digital signal processor (DSP), and a DSP memory. The emulated UART provides a compatible UART-like front end for interlacing directly with a host system and additionally performs direct memory access-like (DMA) functions enabling the direct transfer of transmit data between the host system and DSP memory that is directly accessible by the DSP for modulation and/or other processing such as data compression. The emulated UART module additionally provides performance features such as adjustable buffering quantity thresholds for triggering interrupts to either the host system or DSP, and pacing features that provide the host system with the appearance and performance of a serialized UART.

Abstract translation: 一种用于经由通信模块在主机系统和通信网络之间传送数据的装置和方法，其中通信模块向主机系统呈现类似UART的接口。 通信模块由模拟UART模块，数字信号处理器（DSP）和DSP存储器组成。 仿真UART提供了一个兼容的类似UART的前端，用于与主机系统直接交织，并且还执行直接存储器访问（DMA）功能，使得能够在主机系统和DSP存储器之间直接传输发送数据，这些数据可由 DSP用于调制和/或其他处理，如数据压缩。 仿真UART模块还提供了性能特征，例如可调节缓冲量阈值，用于触发主机系统或DSP的中断，以及为主机系统提供串行化UART的外观和性能的起搏功能。

公开(公告)号：US06338077B1

公开(公告)日：2002-01-08

申请号：US09321899

申请日：1999-05-28

Applicant: Spiro Poulis ,  John Evans ,  Shayne Messerly

Inventor： Spiro Poulis ,  John Evans ,  Shayne Messerly

IPC: G06J100

CPC classification number: H03H17/02

Abstract: A system and circuit is provided for digitally synthesizing the impedance of a transfer function. The impedance of the transfer function is digitally synthesized by generating a current that, when combined with an input voltage, results in the impedance of the transfer function. This is accomplished by sensing the input signal and processing it with a generator or multiplier such that a voltage is produced. The produced voltage controls a current source and creates a current having a value equal to the inverse of the transfer function impedance. The sensed or input voltage divided by the generated current is equal to the impedance of the transfer function. In this manner, many different transfer functions can be digitally synthesized without having to design an alternate circuit.

Abstract translation: 提供了一种用于数字合成传递函数的阻抗的系统和电路。 传递函数的阻抗通过产生与输入电压组合导致传递函数的阻抗的电流数字合成。 这通过感测输入信号并用发生器或乘法器来处理，从而产生电压来实现。 产生的电压控制电流源并产生具有等于传递函数阻抗的倒数的值的电流。 感测或输入电压除以发电电流等于传递函数的阻抗。 以这种方式，可以数字地合成许多不同的传递函数，而不必设计备用电路。

公开(公告)号：US08472614B2

公开(公告)日：2013-06-25

申请号：US12644201

申请日：2009-12-22

Applicant: Spiro Poulis ,  John Evans ,  Shayne Messerly

Inventor： Spiro Poulis ,  John Evans ,  Shayne Messerly

IPC: H04M1/00 ,  H04M9/00

CPC classification number: H04M1/7385 ,  H04M11/066

Abstract: The present invention discloses circuits for isolating and attenuating signals generated by a telephone network. In disclosed embodiments, a metering pulse signal is isolated from the terminals of the connecting device, and then attenuated with an impedance that is synthesized with a programmable digital signal processor. Embodiments also utilize the digital signal processor to synthesize a termination impedance for the connecting device. The termination impedance matches closely the characteristic impedance of the network, so as to minimize wave reflections and the like.

Abstract translation: 本发明公开了一种用于隔离和衰减由电话网络产生的信号的电路。 在所公开的实施例中，计量脉冲信号与连接装置的端子隔离，然后用与可编程数字信号处理器合成的阻抗衰减。 实施例还利用数字信号处理器来合成连接装置的终端阻抗。 终端阻抗与网络的特性阻抗密切相关，以便最小化波反射等。

公开(公告)号：US20100119056A1

公开(公告)日：2010-05-13

申请号：US12644201

申请日：2009-12-22

Applicant: Spiro POULIS ,  John EVANS ,  Shayne MESSERLY

Inventor： Spiro POULIS ,  John EVANS ,  Shayne MESSERLY

IPC: H04M1/00

CPC classification number: H04M1/7385 ,  H04M11/066

Abstract: The present invention discloses circuits for isolating and attenuating signals generated by a telephone network. In disclosed embodiments, a metering pulse signal is isolated from the terminals of the connecting device, and then attenuated with an impedance that is synthesized with a programmable digital signal processor. Embodiments also utilize the digital signal processor to synthesize a termination impedance for the connecting device. The termination impedance matches closely the characteristic impedance of the network, so as to minimize wave reflections and the like.

Abstract translation: 本发明公开了一种用于隔离和衰减由电话网络产生的信号的电路。 在所公开的实施例中，计量脉冲信号与连接装置的端子隔离，然后用与可编程数字信号处理器合成的阻抗衰减。 实施例还利用数字信号处理器来合成连接装置的终端阻抗。 终端阻抗与网络的特性阻抗密切相关，以便最小化波反射等。

公开(公告)号：US06567472B1

公开(公告)日：2003-05-20

申请号：US09320485

申请日：1999-05-26

Applicant: Spiro Poulis ,  John Evans

Inventor： Spiro Poulis ,  John Evans

IPC: H04B308

CPC classification number: H04L25/0278 ,  H04L25/0272

Abstract: The present invention provides a line termination circuit for matching the characteristic impedance of a transmission line, or more generally, a network. The present invention receives the voltage as present on the transmission line and attenuates it such that circuit components rated for lower voltages may be used to produce the reflected impedance. The attenuated voltage is placed across a scaled impedance which results in a reflected impedance substantially equal to the characteristic impedance of the transmission line. The line termination circuit uses a feedback loop to reflect the ground referenced scaled impedance across the transmission lines. The circuit generates a current having a value of one over the characteristic impedance of the network, which ensures that the reflected impedance, from the network, is substantially equal to the characteristic impedance of the network.

Abstract translation: 本发明提供一种线路终端电路，用于匹配传输线路的特征阻抗，或更一般地，网络。 本发明接收存在于传输线上的电压并使其衰减，使得额定为较低电压的电路组件可用于产生反射阻抗。 衰减的电压跨越比例的阻抗放置，导致反射阻抗基本上等于传输线的特性阻抗。 线路终端电路使用反馈回路来反映跨传输线路的地面参考的按比例的阻抗。 该电路产生一个超过网络的特性阻抗值的电流，这确保了来自网络的反射阻抗基本上等于网络的特性阻抗。

公开(公告)号：US06377667B1

公开(公告)日：2002-04-23

申请号：US09268610

申请日：1999-03-15

Applicant: Spiro Poulis ,  John Evans ,  Shane Messerly

Inventor： Spiro Poulis ,  John Evans ,  Shane Messerly

IPC: H04M1100

CPC classification number: H04L12/10 ,  H04M11/06

Abstract: A power management circuit for use in a terminal interface device such as a modem which converts available power from a terminal or host device such as a computer into usable standby power for use when the terminal interface device is non-operational. The power management circuit is additionally comprised of a voltage regulator which, when a terminal interface device becomes operational, is enabled and regulates available voltage and current into usable power as available from the interfacing communication network. The preferred embodiment of the power management circuit is further comprised of a programmable hold current generator which enables a terminal interface device incorporating the power management circuit to be compatible with multiple communication networks having diverse hold current specifications. The use of power available from the communication network in generating the operational voltage greatly reduces interference injected onto the communication network.

Abstract translation: 一种用于诸如调制解调器的终端接口设备的电源管理电路，其将终端或诸如​​计算机的主机设备的可用功率转换为当终端接口设备不可操作时使用的可用备用电力。 电源管理电路还包括电压调节器，当终端接口设备变得可操作时，电压调节器被启用，并且将可用的电压和电流调节到可从接口通信网络获得的可用功率。 功率管理电路的优选实施例还包括可编程保持电流发生器，其使得结合功率管理电路的终端接口设备能够与具有不同保持电流规格的多个通信网络兼容。 在通信网络中使用可用于产生操作电压的电力大大降低了注入到通信网络上的干扰。

公开(公告)号：US06700387B1

公开(公告)日：2004-03-02

申请号：US10449636

申请日：2003-05-30

Applicant: Spiro Poulis ,  John Evans ,  Shayne Messerly

Inventor： Spiro Poulis ,  John Evans ,  Shayne Messerly

IPC: G01R3108

CPC classification number: H04B1/58

Abstract: The present invention synthesizes a prescribed impedance. The impedance is synthesized by generating a current having a value substantially equal to a voltage divided by a prescribed impedance. Sensing the line voltage and converting that sensed line voltage to its digital equivalent accomplish this first step. The digital line voltage is processed by a factor related to the prescribed impedance to produce an output voltage that has a value substantially equal to the sensed voltage divided by the prescribed impedance. The output voltage controls a voltage to current converter that generates the appropriate current across the points or terminals where the line voltage was measured. Thus, the prescribed impedance is generated across these points or terminals because the line voltage divided by the generated current is substantially equal to the prescribed impedance.

Abstract translation: 本发明合成规定的阻抗。 通过产生具有基本上等于被规定阻抗除以的电压的值的电流来合成阻抗。 感测线路电压并将感测到的线路电压转换为其数字等效电压完成了第一步。 数字线路电压由与规定阻抗相关的因子处理，以产生具有基本上等于感测电压除以规定阻抗的值的输出电压。 输出电压控制电压到电流转换器，其在测量线路电压的点或端子处产生适当的电流。 因此，由于产生的电流除以的线电压基本上等于规定的阻抗，所以在这些点或端子之间产生规定的阻抗。

公开(公告)号：US06573729B1

公开(公告)日：2003-06-03

申请号：US09649188

申请日：2000-08-28

Applicant: Spiro Poulis ,  John Evans ,  Shayne Messerly

Inventor： Spiro Poulis ,  John Evans ,  Shayne Messerly

IPC: G01R3102

CPC classification number: H04B1/58

Abstract: The present invention synthesizes a prescribed impedance. The impedance is synthesized by generating a current having a value substantially equal to a voltage divided by a prescribed impedance. Sensing the line voltage and converting that sensed line voltage to its digital equivalent accomplish this first step. The digital line voltage is processed by a factor related to the prescribed impedance to produce an output voltage that has a value substantially equal to the sensed voltage divided by the prescribed impedance. The output voltage controls a voltage to current converter that generates the appropriate current across the points or terminals where the line voltage was measured. Thus, the prescribed impedance is generated across these points or terminals because the line voltage divided by the generated current is substantially equal to the prescribed impedance.

Abstract translation: 本发明合成规定的阻抗。 通过产生具有基本上等于被规定阻抗除以的电压的值的电流来合成阻抗。 感测线路电压并将感测到的线路电压转换为其数字等效电压完成了第一步。 数字线路电压由与规定阻抗相关的因子处理，以产生具有基本上等于感测电压除以规定阻抗的值的输出电压。 输出电压控制电压到电流转换器，其在测量线路电压的点或端子处产生适当的电流。 因此，由于产生的电流除以的线电压基本上等于规定的阻抗，所以在这些点或端子之间产生规定的阻抗。

公开(公告)号：US6128311A

公开(公告)日：2000-10-03

申请号：US31103

申请日：1998-02-26

Applicant: Spiro Poulis ,  David M. Arnesen

Inventor： Spiro Poulis ,  David M. Arnesen

IPC: G06F13/42 ,  H04L12/66

CPC classification number: G06F13/4286

Abstract: A method and apparatus for interconnecting via a serial bus a master processor and a co-processor having directly interfaceable parallel interfaces thereby accommodating the remote location of the co-processor from the master processor. The master processor interfaces with a serial bus interface for converting the parallel interface of the master processor into a serial interface forming a serial bus including a serial data out signal, a serial data in signal, a serial clock signal and a frame sync signal. The serial bus interfaces with the remote module having the co-processor located therein. The serial bus interfaces directly with an interface controller for converting the serial information back to a parallel format compatable with the requirements of the co-processor's parallel interface. The interface controller is further capable of generating control signals such as resets and general purpose outputs when directed by the master processor and reading status of the co-processor when also directed by the master processor. Testing functionality is also included for specific incorporation of an ISDN-specific I/O interface device functioning as the co-processor.

Abstract translation: 一种用于经由串行总线互连主处理器和具有直接可接口的并行接口的协处理器的方法和装置，从而从主处理器容纳协处理器的远程位置。 主处理器与串行总线接口连接，用于将主处理器的并行接口转换成串行接口，形成串行数据输出信号，信号串行数据，串行时钟信号和帧同步信号的串行总线。 串行总线与位于其中的协处理器的远程模块接口。 串行总线直接与接口控制器接口，用于将串行信息转换为与协处理器并行接口的要求相兼容的并行格式。 当由主处理器指导时，接口控制器还能够产生诸如复位和通用输出的控制信号，并且当主处理器也指示时，该协处理器的读取状态。 还包括测试功能，用于特定并入用作协处理器的ISDN专用I / O接口设备。