System and method for combat simulation
    2.
    发明授权
    System and method for combat simulation 有权
    作战模拟系统和方法

    公开(公告)号:US07052276B2

    公开(公告)日:2006-05-30

    申请号:US10250970

    申请日:2002-01-03

    IPC分类号: F41A33/00

    CPC分类号: F41G3/2655 F41G3/26

    摘要: The invention relates to simulation of effects in a combat environment, wherein personnel, vehicles and buildings are exposed to simulated fire from military weapons. Direct fire and indirect fire are simulated by means of at least one of light rays and radio waves. Effects of attacking fire are registered by means of a target object device, which includes sensors adapted to detect the light rays respective the radio waves and are co-located with the target object (140). According to the invention the target object is associated to at least one protecting object located between the simulated fire and the target object if such object exists in the current combat situation. This enables a consideration to various protecting object— influence on the simulated fire and the effects on corresponding actual fire. The invention thereby simulates the effects of direct fire and indirect fire in a realistic manner, which in turn provides good chances of an adequate behavior of the training personnel in a corresponding live situation.

    摘要翻译: 本发明涉及在战斗环境中的效果的模拟,其中人员,车辆和建筑物暴露于来自军事武器的模拟火灾。 通过光线和无线电波中的至少一种来模拟直接火灾和间接火灾。 通过目标对象装置来记录攻击的效果,目标对象装置包括适于检测无线电波的光线并与目标对象(140)共处的传感器。 根据本发明,如果在目前的作战情况下存在这样的对象,则目标对象与位于模拟的火和目标对象之间的至少一个保护对象相关联。 这样可以考虑各种保护物体对模拟火灾的影响以及对相应的实际火灾的影响。 因此,本发明以现实的方式模拟直接火灾和间接火灾的影响,从而在相应的现场情况下提供训练人员的适当行为的良好机会。

    Apparatus and method for generating a predetermined time delay in a semiconductor circuit
    3.
    发明授权
    Apparatus and method for generating a predetermined time delay in a semiconductor circuit 失效
    用于在半导体电路中产生预定时间延迟的装置和方法

    公开(公告)号:US06900683B2

    公开(公告)日:2005-05-31

    申请号:US10433518

    申请日:2000-12-05

    摘要: A semiconductor arrangement is provided for generating a predetermined time delay. Two clocks are connected to two parallel, redundant semi-conductor circuits emitting clock signals from multiplexers. The redundant circuits receive delayed clock signals from one of the clocks, and from the other clock, clock signals that are delayed in adjustable delay circuits to be phased in with the clock signals from the first clock. A number of delay elements and a first reference number of delay elements, providing a predetermined delay time, are connected in a reference delay circuit. A quotient of the two numbers is stored. One of the semi-conductor circuits is replaced by an alternative semi-conductor circuit, the reference delay circuit of which is set on the predetermined delay time, corresponding to a second reference number of delay elements. An adjustable delay circuit is set on the same delay time as the replaced semi-conductor circuit by means of the second reference number and the quotient.

    摘要翻译: 提供了用于产生预定时间延迟的半导体布置。 两个时钟连接到从多路复用器发射时钟信号的两个并行冗余半导体电路。 冗余电路从其中一个时钟接收延迟的时钟信号,并从另一个时钟接收在可调节延迟电路中延迟的时钟信号,以与第一个时钟的时钟信号相对准。 在参考延迟电路中连接多个延迟元件和提供预定延迟时间的第一参考数量的延迟元件。 存储两个数字的商。 半导体电路中的一个被替代的半导体电路替代,其中参考延迟电路被设置在预定延迟时间上,对应于第二参考数量的延迟元件。 通过第二参考号和商,在与替换的半导体电路相同的延迟时间上设置可调延迟电路。