公开(公告)号：US5925869A

公开(公告)日：1999-07-20

申请号：US932756

申请日：1997-09-17

申请人： Stephen E. Still ,  Ira Baker ,  Neal William Horner ,  James J. Tout, Jr.

发明人： Stephen E. Still ,  Ira Baker ,  Neal William Horner ,  James J. Tout, Jr.

IPC分类号： G06K7/10

CPC分类号： G06K7/10851

摘要： A multiple-input, mixed-type bar code processor, comprising: a plurality of retriggerable pulse generators, each having data inputs coupled to sources of potential representing fixed logic levels and each having at least one of a clear and a reset input coupled to a different one of a plurality of sources of input bar code data streams, for regenerating the input bar code data streams responsive to logic level transitions of the input bar code data streams, both when any input bar code data stream is logically low absent scanned data and when any other input bar code data stream is logically high absent the scanned data; a circuit for receiving all of the regenerated bar code data streams and generating a single output bar code data stream; and, a bar code data stream decoder coupled for receiving the single output bar code data stream. A method for processing multiple-input, mixed-type bar codes comprises the steps of: independently generating retriggerable pulses responsive to different ones of a plurality of input bar code data streams, at least one of which is logically low absent scanned data and at least one other of which is logically high absent scanned data; generating the retriggerable pulses with a width greater than a maximum time interval between logic level transitions within any of group of pulses in the bar code data streams corresponding to a single bar code read; and, combining all of the regenerated bar code data streams into a single output bar code data stream.

摘要翻译： 一种多输入混合型条形码处理器，包括：多个可再触发脉冲发生器，每个脉冲发生器具有耦合到表示固定逻辑电平的电位源的数据输入，并且每个具有耦合到一个或多个的清零和复位输入中的至少一个 输入条形码数据流的多个源中的不同的一个，用于响应于输入条形码数据流的逻辑电平转换再生输入条形码数据流，当任何输入条形码数据流在逻辑上较低时，不存在扫描数据， 当任何其他输入条形码数据流在逻辑上高时，不存在扫描数据; 用于接收所有再生的条形码数据流并产生单个输出条形码数据流的电路; 以及被耦合用于接收单个输出条形码数据流的条形码数据流解码器。 一种用于处理多输入混合型条形码的方法，包括以下步骤：响应于多个输入条形码数据流中的不同的输入条形码数据流独立产生可再触发脉冲，其中至少一个在逻辑上不存在扫描数据，并且至少 另外一个是没有扫描数据的逻辑高; 产生可再触发脉冲，其宽度大于对应于单个条形码读取的条形码数据流中任一组脉冲内的逻辑电平转换之间的最大时间间隔; 以及将所有再生的条形码数据流组合成单个输出条形码数据流。

公开(公告)号：US20140033120A1

公开(公告)日：2014-01-30

申请号：US13558442

申请日：2012-07-26

申请人： David BENTAL ,  Joel M. Antolini ,  Zinovii Dmytriv ,  Kenneth M. Klee ,  Kenneth A. Koster ,  Joseph U. Romaine ,  Matthew A. Schnitz ,  Stephen E. Still

发明人： David BENTAL ,  Joel M. Antolini ,  Zinovii Dmytriv ,  Kenneth M. Klee ,  Kenneth A. Koster ,  Joseph U. Romaine ,  Matthew A. Schnitz ,  Stephen E. Still

IPC分类号： G06F3/048

CPC分类号： G06F16/00 ,  G06Q10/02 ,  G06Q30/02 ,  G06Q30/0201 ,  G06Q30/0643

摘要： Methods and apparatus for conducting market analyses on data drawn from various one or more sources for conducting airline travel and cargo market analyses and the presentation of analysis results using intuitive graphical user interfaces. Data is displayed in a visual dashboard having plural dashboard panes for interfacing an associated user with a plurality of associated databases. Data is presented to an associated user from at least one associated database in drill down enabled hierarchical levels. A user is presented with data from associated firewall protected and non-firewall protected databases in selectable merged visual formats.

摘要翻译： 对从各种一个或多个来源进行航空旅行和货运市场分析的数据进行市场分析的方法和装置，以及使用直观的图形用户界面呈现分析结果。 数据显示在具有多个仪表板窗格的视觉仪表板中，用于将相关用户与多个相关联的数据库进行接口。 从下拉启用的层次级别中，数据从至少一个关联的数据库呈现给相关联的用户。 以可选择的合并视觉格式向用户显示来自相关防火墙和非防火墙保护数据库的数据。

公开(公告)号：US06691235B1

公开(公告)日：2004-02-10

申请号：US09627093

申请日：2000-07-27

申请人： Ray Garcia ,  Warren F. Huber ,  Kendall A. Honeycutt ,  Stephen E. Still

发明人： Ray Garcia ,  Warren F. Huber ,  Kendall A. Honeycutt ,  Stephen E. Still

IPC分类号： G06F126

CPC分类号： G06F1/26

摘要： Apparatus for providing electrical power to a processor (CPU) within a computing system includes a fixed-voltage power supply and a programmable power supply. When the computing system is turned on, a switching circuit determines whether the processor is a unified voltage plane type, having a first particular pin electrically floating, or a split voltage plane type, having this pin grounded. In either case, the output of the programmable power supply is applied to the pins associated with the core voltage plane of a split voltage plane type. If the processor is a unified voltage plane type, the switching circuit applies the output of the programmable power supply to the pins associated with the I/O voltage plane of a split voltage plane type. If it is of a split voltage plane type, the switching circuit applies the output of the fixed-voltage power supply to an I/O voltage plane of the processor, with the programmable power supply being first set to generate a voltage determined by whether a second grounded pin is present in the processor. Then, an instruction in an initialization program causes the processor having a split voltage plane to transmit an identification code, which is used to determine a final level of the programmable power supply voltage.

摘要翻译： 用于向计算系统内的处理器（CPU）提供电力的设备包括固定电压电源和可编程电源。 当计算系统被打开时，开关电路确定处理器是否具有统一的电压平面类型，具有电浮置的第一特定引脚或分离电压平面类型，该引脚接地。 在任一情况下，可编程电源的输出被施加到与分压电压平面类型的核心电压平面相关联的引脚。 如果处理器是统一的电压平面类型，则开关电路将可编程电源的输出施加到与分压电压平面类型的I / O电压平面相关联的引脚。 如果是分压电压平面类型，则开关电路将固定电压电源的输出施加到处理器的I / O电压平面，其中可编程电源首先被设置为产生由一个 处理器中存在第二个接地引脚。 然后，初始化程序中的指令使具有分离电压平面的处理器发送用于确定可编程电源电压的最终电平的识别码。

公开(公告)号：US06400113B1

公开(公告)日：2002-06-04

申请号：US09619235

申请日：2000-07-19

申请人： Ray Garcia ,  Will E. Hamel ,  Kendall A. Honeycutt ,  Stephen E. Still

发明人： Ray Garcia ,  Will E. Hamel ,  Kendall A. Honeycutt ,  Stephen E. Still

IPC分类号： H02P500

CPC分类号： F04D27/001 ,  Y10S388/912

摘要： Apparatus for monitoring fan speeds within a computing system includes a tachometer turning with the fan, providing a tachometer signal including a number of pulses during each revolution of the fan. This tachometer signal is provided as an input to a signal generator in the form of a flip-flop, which generates a square-wave signal having transitions between high and low levels corresponding to tachometer signal pulses. The square-wave signals are provided as inputs to separate input ports of a microprocessor. These input ports are sequentially sampled at a rate providing at least two samples per period of the fastest square-wave signal, so that transitions of each square wave signal during a predetermined time interval can be detected and counted. For each input port, the number of counted transitions is compared to a stored acceptable value to establish whether the fan is operating in an acceptable speed range.

摘要翻译： 用于监测计算系统内的风扇速度的装置包括用风扇转动的转速计，在风扇的每转期间提供包括多个脉冲的转速计信号。 该转速计信号作为触发器形式的信号发生器的输入提供，其产生具有对应于转速计信号脉冲的高电平和低电平之间的转变的方波信号。 方波信号被提供作为微处理器的单独输入端口的输入。 这些输入端口以提供每个最快方波信号的每个周期的至少两个采样的速率被顺序采样，从而可以检测并计数在预定时间间隔期间每个方波信号的转变。 对于每个输入端口，将计数的转换次数与存储的可接受值进行比较，以确定风扇是否在可接受的速度范围内运行。

公开(公告)号：US06240476B1

公开(公告)日：2001-05-29

申请号：US09137490

申请日：1998-08-21

申请人： Ray Garcia ,  Stephen E. Still ,  Kendall A. Honeycutt

发明人： Ray Garcia ,  Stephen E. Still ,  Kendall A. Honeycutt

IPC分类号： G06F1336

CPC分类号： G06F13/364

摘要： A computer system includes a system bus, peripheral devices, bus control logic having bus control lines for bus master operation, and an allocation control circuit. The allocation control circuit is connected to at least one of the bus control lines and at least two of the peripheral devices. The connected bus control line is coupled to one of the connected peripheral devices by the allocation unit so that the one connected peripheral device can operate as a bus master on the system bus. In a preferred embodiment, the allocation control circuit includes switches that are controlled by the system software. Also provided is a method of allocating bus master control lines to peripheral devices. According to the method, the bus master control lines and the peripheral devices are connected to an allocation unit. It is determined which peripheral devices to connect to which bus master control lines, and the allocation unit is directed to couple each bus master control line to one of the peripheral devices so that the selected peripheral devices can operate as bus masters. In a preferred method, the determination is based on user preferences and/or system-detected peripheral devices, and the system software controls the allocation unit.

摘要翻译： 计算机系统包括系统总线，外围设备，具有用于总线主机操作的总线控制线的总线控制逻辑和分配控制电路。 分配控制电路连接到至少一个总线控制线和至少两个外围设备。 连接的总线控制线通过分配单元耦合到所连接的外围设备之一，使得一个连接的外围设备可以作为系统总线上的总线主机工作。 在优选实施例中，分配控制电路包括由系统软件控制的开关。 还提供了一种将总线主控制线分配给外围设备的方法。 根据该方法，总线主控制线和外围设备连接到分配单元。 确定哪些外围设备连接到哪些总线主控制线，并且分配单元被指示将每个总线主控制线连接到外围设备之一，使得所选择的外围设备可以作为总线主控器工作。 在优选方法中，该确定基于用户偏好和/或系统检测的外围设备，并且系统软件控制分配单元。