公开(公告)号：US20170329883A1

公开(公告)日：2017-11-16

申请号：US15663778

申请日：2017-07-30

申请人： OLIVER T. OBERG ,  STEVEN B. SHAUCK

发明人： OLIVER T. OBERG ,  STEVEN B. SHAUCK

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5022 ,  G06F17/5045

摘要： One example includes an RQL circuit simulation system. The system includes a circuit design tool that facilitates user inputs to design an RQL circuit design comprising at least one predetermined RQL circuit design component. The system also includes a memory system that stores the RQL circuit design and an RQL component library comprising predetermined RQL circuit design components from which the at least one predetermined RQL circuit design component is selected. Each of the predetermined RQL circuit design components includes predetermined RQL component metrics associated with performance of the respective one of the predetermined RQL circuit design components. The system also includes a circuit simulator configured to compile performance metrics associated with the RQL circuit design based on the predetermined RQL component metrics associated with the respective at least one of the predetermined RQL circuit design components and to simulate the RQL circuit design based on the performance metrics.

公开(公告)号：US20160370822A1

公开(公告)日：2016-12-22

申请号：US14746377

申请日：2015-06-22

申请人： JOSHUA A. STRONG ,  ANNA Y. HERR ,  QUENTIN P. HERR ,  STEVEN B. SHAUCK

发明人： JOSHUA A. STRONG ,  ANNA Y. HERR ,  QUENTIN P. HERR ,  STEVEN B. SHAUCK

IPC分类号： G06F1/10

摘要： One embodiment includes a clock distribution system. The system includes a standing-wave resonator configured to receive and to resonate a sinusoidal clock signal. The standing-wave resonator includes at least one anti-node portion associated with a peak current amplitude of the sinusoidal clock signal. The system also includes at least one clock line interconnecting each of the at least one anti-node portion and an associated circuit. The at least one clock line can be configured to propagate the sinusoidal clock signal for timing functions associated with the associated circuit.

摘要翻译： 一个实施例包括时钟分配系统。 该系统包括被配置为接收和谐振正弦时钟信号的驻波谐振器。 驻波共振器包括与正弦时钟信号的峰值电流幅度相关联的至少一个反节点部分。 该系统还包括互连至少一个反节点部分和相关电路中的每一个的至少一个时钟线。 至少一个时钟线可被配置为传播用于与相关电路相关联的定时功能的正弦时钟信号。

公开(公告)号：US10520974B2

公开(公告)日：2019-12-31

申请号：US14746377

申请日：2015-06-22

申请人： Joshua A. Strong ,  Anna Y. Herr ,  Quentin P. Herr ,  Steven B. Shauck

发明人： Joshua A. Strong ,  Anna Y. Herr ,  Quentin P. Herr ,  Steven B. Shauck

IPC分类号： G06F1/10 ,  G06F1/04 ,  G06F1/32 ,  G06F1/03 ,  G06F13/42

摘要： One embodiment includes a clock distribution system. The system includes a standing-wave resonator configured to receive and to resonate a sinusoidal clock signal. The standing-wave resonator includes at least one anti-node portion associated with a peak current amplitude of the sinusoidal clock signal. The system also includes at least one clock line interconnecting each of the at least one anti-node portion and an associated circuit. The at least one clock line can be configured to propagate the sinusoidal clock signal for timing functions associated with the associated circuit.

公开(公告)号：US09767238B2

公开(公告)日：2017-09-19

申请号：US14799172

申请日：2015-07-14

申请人： Oliver T. Oberg ,  Steven B. Shauck

发明人： Oliver T. Oberg ,  Steven B. Shauck

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5022 ,  G06F17/5045

摘要： One example includes an RQL circuit simulation system. The system includes a circuit design tool that facilitates user inputs to design an RQL circuit design comprising at least one predetermined RQL circuit design component. The system also includes a memory system that stores the RQL circuit design and an RQL component library comprising predetermined RQL circuit design components from which the at least one predetermined RQL circuit design component is selected. Each of the predetermined RQL circuit design components includes predetermined RQL component metrics associated with performance of the respective one of the predetermined RQL circuit design components. The system also includes a circuit simulator configured to compile performance metrics associated with the RQL circuit design based on the predetermined RQL component metrics associated with the respective at least one of the predetermined RQL circuit design components and to simulate the RQL circuit design based on the performance metrics.

公开(公告)号：US09652571B2

公开(公告)日：2017-05-16

申请号：US14526904

申请日：2014-10-29

申请人： Steven B. Shauck ,  Gary L. Phifer

发明人： Steven B. Shauck ,  Gary L. Phifer

IPC分类号： G06F17/50 ,  H03K3/38 ,  G06N99/00

CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/06 ,  G06N99/002 ,  H03K3/38

摘要： One embodiment of the invention includes a method for generating a Reciprocal Quantum Logic (RQL) circuit design via a synthesis tool. The method includes providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool. The method also includes generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and a component library. The method also includes separating the circuit system into circuit subsystems that are each associated with a separate respective phase of a clock signal via the synthesis tool based on inputs. The method further includes removing the flip-flop device placeholder from the RQL netlist circuit via the synthesis tool to generate the RQL circuit design from the RQL netlist circuit.

公开(公告)号：US20170053045A1

公开(公告)日：2017-02-23

申请号：US15340324

申请日：2016-11-01

申请人： STEVEN B. SHAUCK ,  GARY L. PHIFER

发明人： STEVEN B. SHAUCK ,  GARY L. PHIFER

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/06 ,  G06N99/002 ,  H03K3/38

摘要： One embodiment of the invention includes a method for generating a Reciprocal Quantum Logic (RQL) circuit design via a synthesis tool. The method includes providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool. The method also includes generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and a component library. The method also includes separating the circuit system into circuit subsystems that are each associated with a separate respective phase of a clock signal via the synthesis tool based on inputs. The method further includes removing the flip-flop device placeholder from the RQL netlist circuit via the synthesis tool to generate the RQL circuit design from the RQL netlist circuit.

摘要翻译： 本发明的一个实施例包括通过综合工具生成交互量子逻辑（RQL）电路设计的方法。 该方法包括提供与RQL电路设计的行为和约束相关联的数据以及向综合工具提供的组件库。 该方法还包括生成RQL网表电路，其包括触发器设备占位符和电路系统，所述触发器设备占位符和电路系统经由所述综合工具基于所述数据和组件库耦合到所述触发器设备占位符的输入和输出中的至少一个 。 该方法还包括基于输入将电路系统分离成电路子系统，每个电路子系统通过综合工具分别与时钟信号的单独的相位相关联。 该方法还包括通过综合工具从RQL网表电路去除触发器设备占位符，以从RQL网表电路生成RQL电路设计。

公开(公告)号：US20160125102A1

公开(公告)日：2016-05-05

申请号：US14526904

申请日：2014-10-29

申请人： STEVEN B. SHAUCK ,  GARY L. PHIFER

发明人： STEVEN B. SHAUCK ,  GARY L. PHIFER

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/06 ,  G06N99/002 ,  H03K3/38

摘要： One embodiment of the invention includes a method for generating a Reciprocal Quantum Logic (RQL) circuit design via a synthesis tool. The method includes providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool. The method also includes generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and a component library. The method also includes separating the circuit system into circuit subsystems that are each associated with a separate respective phase of a clock signal via the synthesis tool based on inputs. The method further includes removing the flip-flop device placeholder from the RQL netlist circuit via the synthesis tool to generate the RQL circuit design from the RQL netlist circuit.

摘要翻译： 本发明的一个实施例包括通过综合工具生成交互量子逻辑（RQL）电路设计的方法。 该方法包括提供与RQL电路设计的行为和约束相关联的数据以及向综合工具提供的组件库。 该方法还包括生成RQL网表电路，其包括触发器设备占位符和电路系统，所述触发器设备占位符和电路系统经由所述综合工具基于所述数据和组件库耦合到所述触发器设备占位符的输入和输出中的至少一个 。 该方法还包括基于输入将电路系统分离成电路子系统，每个电路子系统通过综合工具分别与时钟信号的单独的相位相关联。 该方法还包括通过综合工具从RQL网表电路去除触发器设备占位符，以从RQL网表电路生成RQL电路设计。

公开(公告)号：US10339239B2

公开(公告)日：2019-07-02

申请号：US15663778

申请日：2017-07-30

申请人： Oliver T. Oberg ,  Steven B. Shauck

发明人： Oliver T. Oberg ,  Steven B. Shauck

IPC分类号： G06F17/50

摘要： One example includes an RQL circuit simulation system. The system includes a circuit design tool that facilitates user inputs to design an RQL circuit design comprising at least one predetermined RQL circuit design component. The system also includes a memory system that stores the RQL circuit design and an RQL component library comprising predetermined RQL circuit design components from which the at least one predetermined RQL circuit design component is selected. Each of the predetermined RQL circuit design components includes predetermined RQL component metrics associated with performance of the respective one of the predetermined RQL circuit design components. The system also includes a circuit simulator configured to compile performance metrics associated with the RQL circuit design based on the predetermined RQL component metrics associated with the respective at least one of the predetermined RQL circuit design components and to simulate the RQL circuit design based on the performance metrics.

公开(公告)号：US09876505B1

公开(公告)日：2018-01-23

申请号：US15256213

申请日：2016-09-02

申请人： Haitao O. Dai ,  Quentin P. Herr ,  Steven B. Shauck ,  Anna Y. Herr ,  Randall M. Burnett

发明人： Haitao O. Dai ,  Quentin P. Herr ,  Steven B. Shauck ,  Anna Y. Herr ,  Randall M. Burnett

IPC分类号： H03K19/195 ,  G06N99/00 ,  H04B1/40

CPC分类号： H03K19/195 ,  G06N99/002 ,  H03K3/38 ,  H03K19/1952 ,  H04B1/40

摘要： An isochronous receiver system is provided and includes a single flux quantum (SFQ) receiver to receive a data signal from a transmission line. The single flux quantum receiver then converts the data signal to an SFQ signal. The system also includes a converter system to convert the SFQ signal to a reciprocal quantum logic (RQL) signal and to phase-align the RQL signal with a sampling phase of an AC clock signal.

公开(公告)号：US20170017742A1

公开(公告)日：2017-01-19

申请号：US14799172

申请日：2015-07-14

申请人： OLIVER T. OBERG ,  STEVEN B. SHAUCK

发明人： OLIVER T. OBERG ,  STEVEN B. SHAUCK

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5022 ,  G06F17/5045

摘要： One example includes an RQL circuit simulation system. The system includes a circuit design tool that facilitates user inputs to design an RQL circuit design comprising at least one predetermined RQL circuit design component. The system also includes a memory system that stores the RQL circuit design and an RQL component library comprising predetermined RQL circuit design components from which the at least one predetermined RQL circuit design component is selected. Each of the predetermined RQL circuit design components includes predetermined RQL component metrics associated with performance of the respective one of the predetermined RQL circuit design components. The system also includes a circuit simulator configured to compile performance metrics associated with the RQL circuit design based on the predetermined RQL component metrics associated with the respective at least one of the predetermined RQL circuit design components and to simulate the RQL circuit design based on the performance metrics.

摘要翻译： 一个例子包括一个RQL电路仿真系统。 该系统包括电路设计工具，其便于用户输入以设计包括至少一个预定的RQL电路设计组件的RQL电路设计。 该系统还包括存储RQL电路设计的存储器系统和包括预定的RQL电路设计组件的RQL组件库，从该RQL电路设计组件中选择至少一个预定的RQL电路设计组件。 每个预定的RQL电路设计组件包括与预定RQL电路设计组件中的相应一个的性能相关联的预定RQL分量度量。 该系统还包括电路模拟器，其被配置为基于与预定RQL电路设计组件中的相应的至少一个RQL电路设计组件相关联的预定RQL分量度量来编译与RQL电路设计相关联的性能度量，并且基于性能来模拟RQL电路设计 指标