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公开(公告)号：US5384747A
公开(公告)日：1995-01-24
申请号：US178496
申请日：1994-01-07
申请人： Steven J. Clohset
发明人： Steven J. Clohset
CPC分类号： G11C5/14 , Y10T307/615
摘要： A circuit that allows an SRAM to automatically switch into low power mode before its power supply voltage input is brought to a lower voltage when the computer is turned off. The circuit includes a device that drives a chip enable input of the SRAM. The device is controlled by a signal indicating whether power is available to the computer system. If the system power is disconnected, the device asserts a low state to the chip enable input of the SRAM. The circuit also includes a device for gradually decreasing the voltage at the power supply voltage input of the SRAM from the system voltage down to the RTC/CMOS memory voltage, which is provided by a separate battery when the computer is shut off. The power supply input voltage is gradually decreased to allow the SRAM enough time to enter into its low power mode. By delaying the switch from the system power supply voltage to the RTC/CMOS memory voltage until it is certain that the SRAM has entered into a low power state, a very small amount of current is drawn from the battery. As a result, the amount of voltage drop across a resistive network connecting the SRAM to the battery is significantly lower, and therefore, the SRAM is able to retain its data.
摘要翻译： 一个允许SRAM在其电源电压输入之前自动切换到低功耗模式的电路在计算机关闭时变为较低电压。 该电路包括驱动SRAM的芯片使能输入的装置。 设备由指示计算机系统是否可用的信号控制。 如果系统电源断开，则器件会将SRAM的芯片使能输入置为低电平状态。 该电路还包括用于逐渐将SRAM的电源电压输入处的电压从系统电压降低到RTC / CMOS存储器电压的装置，RTC / CMOS存储器电压在计算机关闭时由单独的电池提供。 电源输入电压逐渐降低，使SRAM有足够的时间进入低功耗模式。 通过将开关从系统电源电压延迟到RTC / CMOS存储器电压，直到确定SRAM已经进入低功率状态，则从电池抽取非常少量的电流。 因此，将SRAM连接到电池的电阻网络上的电压降明显降低，因此，SRAM能够保留其数据。
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公开(公告)号：US06658533B1
公开(公告)日：2003-12-02
申请号：US09667405
申请日：2000-09-21
申请人： Zohar Bogin , Steven J. Clohset
发明人： Zohar Bogin , Steven J. Clohset
IPC分类号： G06F1200
CPC分类号： G06F12/0804 , G06F12/0897 , G06F2212/304
摘要： A write cache that reduces the number of memory accesses required to write data to main memory. When a memory write request is executed, the request not only updates the relevant location in cache memory, but the request is also directed to updating the corresponding location in main memory. A separate write cache is dedicated to temporarily holding multiple write requests so that they can be organized for more efficient transmission to memory in burst transfers. In one embodiment, all writes within a predefined range of addresses can be written to memory as a group. In another embodiment, entries are held in the write cache until a minimum number of entries are available for writing to memory, and a least-recently-used mechanism can be used to decide which entries to transmit first. In yet another embodiment, partial writes are merged into a single cache line, to be written to memory in a single burst transmission.
摘要翻译： 写缓存，减少将数据写入主内存所需的内存访问次数。 当执行存储器写入请求时，请求不仅更新高速缓冲存储器中的相关位置，而且还要求更新主存储器中的对应位置。 单独的写高速缓存专用于临时保存多个写请求，使得它们可以被组织以在突发传输中更有效地传输到存储器。 在一个实施例中，预定义地址范围内的所有写入可以作为一组写入存储器。 在另一个实施例中，条目被保留在写高速缓存中，直到最少数目的条目可用于写入存储器，并且最近最少使用的机制可以用于决定首先发送哪些条目。 在另一个实施例中，部分写入被合并到单个高速缓存行中，以单个突发传输方式写入存储器。
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3.发明授权Inserting bus inversion scheme in bus path without increased access latency 失效在总线路径中插入总线反演方案，而不增加访问延迟公开(公告)号：US06584526B1
公开(公告)日：2003-06-24
申请号：US09667049
申请日：2000-09-21
IPC分类号： G06F1338
CPC分类号： G06F11/10 , G06F13/4213 , G11C7/1078 , G11C7/1084
摘要： A technique to reduce accumulated latencies in bus transmission time when a bus inversion scheme is employed. The bus inversion scheme inverts all the data bits whenever more than one-half of the data bits are active, so that the bus never has more that one-half of the bits active during a data transfer. This minimizes the number of driver circuits that are actively driving the bus at any given time. Since it takes a certain amount to time to determine if more than one-half of the bits are active, this process can add to overall latency, or data transfer time on the bus. By placing the bus inversion function in parallel with another function that also contributes to bus latency, such as error correction code (ECC) calculation, only the more time-consuming of the two functions will increase bus latency.
摘要翻译： 一种在采用总线反转方案时减少总线传输时间的累积延迟的技术。 每当超过一半的数据位有效时，总线反相方案会反转所有数据位，这样在数据传输过程中，总线从不会有更多的一半位有效。 这样可以最大限度地减少任何给定时间内积极驱动总线的驱动电路的数量。 由于需要一定的时间来确定是否有超过一半的位是活动的，所以该过程可以增加总线上的总延迟或数据传输时间。 通过将总线反转功能与还有助于总线等待时间（如纠错码（ECC））计算的另一个功能并行布置，只有更多的时间消耗这两个功能才能增加总线延迟。
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公开(公告)号：US5623691A
公开(公告)日：1997-04-22
申请号：US339402
申请日：1994-11-14
CPC分类号： G06F3/0607 , G06F11/325 , G06F3/0653 , G06F3/0676 , G11B33/10 , G06F11/3485 , G11B31/00
摘要： A computer system which includes a circuit to monitor the PCI bus master grant lines and provide a disk drive activity signal if an appropriate grant line is activated. The PCI bus master grant lines are combined with mask signals, so that the grant lines not associated with a PCI bus master such as a SCSI controller are ignored. If an unmasked grant line is activated, a down counter is loaded. While the counter is at a non-zero value, a disk drive activity signal is provided. This disk drive activity signal is combined with other disk drive activity signals to drive the disk drive activity LED.
摘要翻译： 一种计算机系统，其包括用于监视PCI总线主机授权线路的电路，并且如果适当的授权线路被激活则提供磁盘驱动器活动信号。 PCI总线主机授权线路与掩码信号组合，从而忽略与PCI总线主机（如SCSI控制器）无关的授权线路。 如果未屏蔽授权行被激活，则加载递减计数器。 当计数器处于非零值时，提供磁盘驱动器活动信号。 此磁盘驱动器活动信号与其他磁盘驱动器活动信号相结合，以驱动磁盘驱动器活动LED。
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公开(公告)号：US5761527A
公开(公告)日：1998-06-02
申请号：US811321
申请日：1997-03-04
CPC分类号： G06F3/0607 , G06F11/325 , G06F3/0653 , G06F3/0676 , G11B33/10 , G06F11/3485 , G11B31/00
摘要： A computer system which includes a circuit to monitor the PCI bus master grant lines and provide a disk drive activity signal if an appropriate grant line is activated. The PCI bus master grant lines are combined with mask signals, so that the grant lines not associated with a PCI bus master such as a SCSI controller are ignored. If an unmasked grant line is activated, a down counter is loaded. While the counter is at a non-zero value, a disk drive activity signal is provided. This disk drive activity signal is combined with other disk drive activity signals to drive the disk drive activity LED.
摘要翻译： 一种计算机系统，其包括用于监视PCI总线主机授权线路的电路，并且如果适当的授权线路被激活则提供磁盘驱动器活动信号。 PCI总线主机授权线路与掩码信号组合，从而忽略与PCI总线主机（如SCSI控制器）无关的授权线路。 如果未屏蔽授权行被激活，则加载递减计数器。 当计数器处于非零值时，提供磁盘驱动器活动信号。 此磁盘驱动器活动信号与其他磁盘驱动器活动信号相结合，以驱动磁盘驱动器活动LED。
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