公开(公告)号：US06658533B1

公开(公告)日：2003-12-02

申请号：US09667405

申请日：2000-09-21

申请人： Zohar Bogin ,  Steven J. Clohset

发明人： Zohar Bogin ,  Steven J. Clohset

IPC分类号： G06F1200

CPC分类号： G06F12/0804 ,  G06F12/0897 ,  G06F2212/304

摘要： A write cache that reduces the number of memory accesses required to write data to main memory. When a memory write request is executed, the request not only updates the relevant location in cache memory, but the request is also directed to updating the corresponding location in main memory. A separate write cache is dedicated to temporarily holding multiple write requests so that they can be organized for more efficient transmission to memory in burst transfers. In one embodiment, all writes within a predefined range of addresses can be written to memory as a group. In another embodiment, entries are held in the write cache until a minimum number of entries are available for writing to memory, and a least-recently-used mechanism can be used to decide which entries to transmit first. In yet another embodiment, partial writes are merged into a single cache line, to be written to memory in a single burst transmission.

摘要翻译： 写缓存，减少将数据写入主内存所需的内存访问次数。 当执行存储器写入请求时，请求不仅更新高速缓冲存储器中的相关位置，而且还要求更新主存储器中的对应位置。 单独的写高速缓存专用于临时保存多个写请求，使得它们可以被组织以在突发传输中更有效地传输到存储器。 在一个实施例中，预定义地址范围内的所有写入可以作为一组写入存储器。 在另一个实施例中，条目被保留在写高速缓存中，直到最少数目的条目可用于写入存储器，并且最近最少使用的机制可以用于决定首先发送哪些条目。 在另一个实施例中，部分写入被合并到单个高速缓存行中，以单个突发传输方式写入存储器。

公开(公告)号：US06584526B1

公开(公告)日：2003-06-24

申请号：US09667049

申请日：2000-09-21

申请人： Zohar Bogin ,  Serafin E. Garcia ,  Steven J. Clohset

发明人： Zohar Bogin ,  Serafin E. Garcia ,  Steven J. Clohset

IPC分类号： G06F1338

CPC分类号： G06F11/10 ,  G06F13/4213 ,  G11C7/1078 ,  G11C7/1084

摘要： A technique to reduce accumulated latencies in bus transmission time when a bus inversion scheme is employed. The bus inversion scheme inverts all the data bits whenever more than one-half of the data bits are active, so that the bus never has more that one-half of the bits active during a data transfer. This minimizes the number of driver circuits that are actively driving the bus at any given time. Since it takes a certain amount to time to determine if more than one-half of the bits are active, this process can add to overall latency, or data transfer time on the bus. By placing the bus inversion function in parallel with another function that also contributes to bus latency, such as error correction code (ECC) calculation, only the more time-consuming of the two functions will increase bus latency.

摘要翻译： 一种在采用总线反转方案时减少总线传输时间的累积延迟的技术。 每当超过一半的数据位有效时，总线反相方案会反转所有数据位，这样在数据传输过程中，总线从不会有更多的一半位有效。 这样可以最大限度地减少任何给定时间内积极驱动总线的驱动电路的数量。 由于需要一定的时间来确定是否有超过一半的位是活动的，所以该过程可以增加总线上的总延迟或数据传输时间。 通过将总线反转功能与还有助于总线等待时间（如纠错码（ECC））计算的另一个功能并行布置，只有更多的时间消耗这两个功能才能增加总线延迟。

公开(公告)号：US20080133952A1

公开(公告)日：2008-06-05

申请号：US11633183

申请日：2006-12-04

申请人： Chai Huat Gan ,  Darren Abramson ,  Zohar Bogin

发明人： Chai Huat Gan ,  Darren Abramson ,  Zohar Bogin

IPC分类号： G06F13/00 ,  G06F1/32

CPC分类号： G06F1/3225

摘要： For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.

摘要翻译： 对于由计算机系统处理的等时数据流，例如高清晰度音频流，实施例跟踪用于数据流的输入和输出缓冲器中的可用空间。 缓冲器中的可用空间确定是否满足各种低功率进入和退出阈值。 如果满足所有低功率入口阈值，则诸如时钟，锁相环和直接介质接口链路的各种电路可能被置于低功率状态，并且数据流控制器进入空闲窗口，使得存储器请求不是 服务。 在此期间，系统DRAM可能会开始刷新。 一旦输入低功率状态，如果满足任何退出阈值，则低功率状态结束。 描述和要求保护其他实施例。

公开(公告)号：US07181605B2

公开(公告)日：2007-02-20

申请号：US10693226

申请日：2003-10-24

申请人： Zohar Bogin ,  Surya Kareenahalli ,  Anoop Mukker ,  David Sastry ,  Tuong Trieu

发明人： Zohar Bogin ,  Surya Kareenahalli ,  Anoop Mukker ,  David Sastry ,  Tuong Trieu

IPC分类号： G06F9/00

CPC分类号： G06F1/24

摘要： A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.

摘要翻译： 已经公开了响应于系统热复位来确定地关闭存储器件的方法。 该方法的一个实施例包括在系统中响应于系统中的第二类型的复位而引起系统中的多个存储器件中的第一类型的复位，如果存储器件未被初始化并且使能存储器中的确定性关断模式 控制器，其在存储器件初始化之后耦合到存储器件。 描述和要求保护其他实施例。

公开(公告)号：US07082480B2

公开(公告)日：2006-07-25

申请号：US10674944

申请日：2003-09-29

申请人： Zohar Bogin ,  Serafin E. Garcia

发明人： Zohar Bogin ,  Serafin E. Garcia

IPC分类号： G06F3/00

CPC分类号： G06F13/24 ,  G06F13/385

摘要： A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.

摘要翻译： 在具有调度器和多个下行命令队列的计算机系统中防止死锁和活动锁的技术的组合。 在一个实施例中，需要在所有受影响的下游命令队列中同时可用空间的广播事务变成延迟的事务，使得命令队列被保留，并且重试其他事务直到广播事务完成。 在另一个实施例中，如果事务在预定时间内未完成，则使用拯救计时器推迟事务。 在另一个实施例中，如果存在小于可用于该事务的预定量的下游缓冲区空间，则潜在地解决由可编程属性映射控制的存储空间的锁定事务被处理为延迟事务。

公开(公告)号：US06983339B1

公开(公告)日：2006-01-03

申请号：US09675801

申请日：2000-09-29

申请人： Jeffrey L. Rabe ,  Satish Acharya ,  Zohar Bogin ,  Serafin E. Garcia ,  David J. Harriman

发明人： Jeffrey L. Rabe ,  Satish Acharya ,  Zohar Bogin ,  Serafin E. Garcia ,  David J. Harriman

IPC分类号： G06F1/00

CPC分类号： G06F13/24

摘要： A method and apparatus for delivering APIC interrupts to a processor, and between processors, as FSB transactions. Interrupts and hardware signals, generated by a PCI device, are converted into an upstream memory write interrupt and further converted into an FSB interrupt transaction, received by a processor. Interrupts marked as lowest priority re-directable are redirected based on task priority information. Support for XTPR transactions to update XTPR registers is provided. Preferred ordering of XTPR update transactions and interrupts to be redirected is provided.

摘要翻译： 一种用于将APIC中断传送到处理器和处理器之间的方法和装置，作为FSB事务。 由PCI设备生成的中断和硬件信号被转换为上游存储器写入中断，并进一步转换为由处理器接收的FSB中断事务。 标记为最低优先级可重定向的中断根据任务优先级信息重定向。 提供对XTPR事务的支持以更新XTPR寄存器。 提供XTPR更新事务和重定向中断的优先顺序。

公开(公告)号：US20050195202A1

公开(公告)日：2005-09-08

申请号：US10796686

申请日：2004-03-08

申请人： David Freker ,  Aditya Sreenivas ,  Zohar Bogin ,  Anoop Mukker ,  Tuong Trieu

发明人： David Freker ,  Aditya Sreenivas ,  Zohar Bogin ,  Anoop Mukker ,  Tuong Trieu

IPC分类号： G06F12/00 ,  G06F12/14 ,  G06F13/00

CPC分类号： G06F13/1684

摘要： Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

摘要翻译： 本发明的实施例涉及使用双通道存储器件的第一通道访问第一对相邻数据块; 并且使用所述存储器件的第二通道同时访问第二对相邻数据块，所述第二对与所述第一对间隔开预定间隔。

公开(公告)号：US20050143843A1

公开(公告)日：2005-06-30

申请号：US10723132

申请日：2003-11-25

申请人： Zohar Bogin ,  Arthur Hunter ,  Krishnamurthy Venkataramana ,  Mihir Shah

发明人： Zohar Bogin ,  Arthur Hunter ,  Krishnamurthy Venkataramana ,  Mihir Shah

IPC分类号： G05B11/01 ,  G10L19/14

CPC分类号： G10L19/167

摘要： Machine-readable media, methods, and apparatus are described to pace commands to codecs. Some embodiments comprise an audio controller that transfers frames to codecs and places commands in the frames at a pace dictated by a command pacer.

摘要翻译： 描述了机器可读介质，方法和装置，以将命令调整到编解码器。 一些实施例包括音频控制器，该音频控制器将帧传送到编解码器，并以由命令起搏器指示的速度将命令放置在帧中。

公开(公告)号：US20050114569A1

公开(公告)日：2005-05-26

申请号：US10723347

申请日：2003-11-25

申请人： Zohar Bogin ,  Brent Chartrand ,  Arthur Hunter

发明人： Zohar Bogin ,  Brent Chartrand ,  Arthur Hunter

IPC分类号： G06F13/16 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： Machine-readable media, methods, and apparatus are described to stream data between a codec and a buffer in system memory and to maintain a value in system memory that is indicative of a current position in the buffer. In some embodiments, an audio controller streams the data across an isochronous channel having relaxed ordering rules to the buffer in the system memory and updates the value indicative of current position via a write across the isochronous channel to the system memory.

摘要翻译： 描述了机器可读介质，方法和装置，以在系统存储器中的编解码器和缓冲器之间流式传输数据，并维持指示缓冲器中当前位置的系统存储器中的值。 在一些实施例中，音频控制器通过具有放松排序规则的同步信道将数据流传输到系统存储器中的缓冲器，并且通过跨同步信道的写入更新指示当前位置的值到系统存储器。

公开(公告)号：US06502150B1

公开(公告)日：2002-12-31

申请号：US09205649

申请日：1998-12-03

申请人： Zohar Bogin ,  Narendra S. Khandekar ,  Steve J. Clohset

发明人： Zohar Bogin ,  Narendra S. Khandekar ,  Steve J. Clohset

IPC分类号： G06F1300

CPC分类号： G06F13/364

摘要： A computer system that includes at least two host agents is provided. The computer system further includes a chipset that includes a resource to be shared by the at least two host agents. The chipset is coupled to the-at least two host agents. The chipset prevents a first host agent, that occupies the shared resource to access the shared resource until a second host agent, has made progress in accessing said shared resource.

摘要翻译： 提供了包括至少两个主机代理的计算机系统。 计算机系统还包括芯片组，其包括要由至少两个主机代理共享的资源。 芯片组耦合到至少两个主机代理。 芯片组防止占用共享资源的第一主机代理访问共享资源，直到第二个主机代理在访问所述共享资源时取得进展。