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    Executing checker instructions in redundant multithreading environments
    4.
    发明申请
    Executing checker instructions in redundant multithreading environments 有权
    在冗余多线程环境中执行检查器指令

    公开(公告)号：US20060095821A1

    公开(公告)日：2006-05-04

    申请号：US10953887

    申请日：2004-09-29

    申请人： Shubhendu Mukherjee ,  Joel Emer ,  Steven Reinhardt ,  Christopher Weaver

    发明人： Shubhendu Mukherjee ,  Joel Emer ,  Steven Reinhardt ,  Christopher Weaver

    IPC分类号： G06F9/44

    CPC分类号： G06F11/1494 ,  G06F11/1695

    摘要： A method and apparatus for a checker instruction in a redundant multithreading environment is described. In one embodiment, when RMT requires, a processor may issue a checker instruction in both a leading thread and a trailing thread. The checker instruction may travel down individual pipelines for each thread independently until it reaches a buffer at the end of each pipeline. Then, prior to committing the checker instruction, the checker instruction looks for its counterpart and does a comparison of the instructions. If the checker instructions match, the checker instructions commit and retires otherwise an error is declared.

    摘要翻译： 描述用于冗余多线程环境中的检查指令的方法和装置。 在一个实施例中，当RMT需要时，处理器可以在前导线程和后退线程中发出校验指令。 检查器指令可以独立地沿着每个线程的各个管道下行，直到它到达每个管道末端的缓冲区。 然后，在提交检查指令之前，检验员指令寻找其对应方，并对指令进行比较。 如果检查器指令匹配，则检查器指令提交并退出，否则声明错误。

    Reducing false error detection in a microprocessor by tracking dynamically dead instructions
    6.
    发明申请
    Reducing false error detection in a microprocessor by tracking dynamically dead instructions 审中-公开
    通过跟踪动态死指令，减少微处理器中的错误检测

    公开(公告)号：US20050283590A1

    公开(公告)日：2005-12-22

    申请号：US10872109

    申请日：2004-06-17

    申请人： Christopher Weaver ,  Shubhendu Mukherjee ,  Joel Emer ,  Steven Reinhardt

    发明人： Christopher Weaver ,  Shubhendu Mukherjee ,  Joel Emer ,  Steven Reinhardt

    IPC分类号： G06F9/38 ,  G06F9/40

    CPC分类号： G06F9/3865

    摘要： A technique to reduce false error detection in microprocessors by tracking dynamically dead instructions. When an instruction commits, it is then stored in a PET buffer. A processor may now declare a machine check error when the instruction is being removed from the PET buffer rather than at the commit point. The processor can scan the PET buffer to determine if the instruction is a dynamically dead instruction. This further enables the processor to reduce false positives.

    摘要翻译： 通过跟踪动态死指令来减少微处理器中的错误检测的技术。 当指令提交时，然后将其存储在PET缓冲器中。 当从PET缓冲区而不是在提交点移除指令时，处理器现在可以声明机器检查错误。 处理器可以扫描PET缓冲区，以确定指令是否是动态死指令。 这进一步使得处理器能够减少误报。

    Hardware recovery in a multi-threaded architecture
    7.
    发明申请
    Hardware recovery in a multi-threaded architecture 有权
    多线程架构中的硬件恢复

    公开(公告)号：US20050050386A1

    公开(公告)日：2005-03-03

    申请号：US10651523

    申请日：2003-08-29

    申请人： Steven Reinhardt ,  Shubhendu Mukherjee ,  Joel Emer

    发明人： Steven Reinhardt ,  Shubhendu Mukherjee ,  Joel Emer

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1482

    摘要： Log-based hardware recovery. A checkpointed state of a system includes both architectural register values and memory. The checkpoint consists of a copy of the architectural register file values at the time the checkpoint is generated. An ordered log of non-deterministic events is maintained so that the responses can be repeated to simulate a complete checkpoint for error recovery purposes. When a processor detects an error, the processor reloads the state from the last checkpoint and repeats the non-deterministic events from the log.

    摘要翻译： 基于日志的硬件恢复。 系统的检查点状态包括体系结构寄存器值和存储器。 检查点由生成检查点时的体系结构寄存器文件值的副本组成。 维护非确定性事件的有序日志，以便重复响应以模拟完整的检查点以进行错误恢复。 当处理器检测到错误时，处理器从上一个检查点重新加载状态，并从日志重复非确定性事件。

    Buffering unchecked stores for fault detection in redundant multithreading systems using speculative memory support
    9.
    发明申请
    Buffering unchecked stores for fault detection in redundant multithreading systems using speculative memory support 审中-公开
    使用推测内存支持，在冗余多线程系统中缓冲未检查的存储，以进行故障检测

    公开(公告)号：US20050193283A1

    公开(公告)日：2005-09-01

    申请号：US10749618

    申请日：2003-12-30

    申请人： Steven Reinhardt ,  Shubhendu Mukherjee ,  Joel Emer ,  Christopher Weaver

    发明人： Steven Reinhardt ,  Shubhendu Mukherjee ,  Joel Emer ,  Christopher Weaver

    IPC分类号： G06F11/14 ,  G06F11/00

    CPC分类号： G06F11/1497

    摘要： A multithreaded architecture is disclosed for buffering unchecked stores for fault detection in redundant multithreading systems using speculative memory support. In particular, the performance of a SRT processor is enhanced by using speculative memory support to buffer the leading threads stores until they can be compared with their trailing thread counterparts. Buffering these stores in the memory system allows them to be removed from the store buffer. Since the speculative memory system will have greater capacity than the store buffer, additional stores may be buffered before the leading thread will be forced to stall. This will result in an increase in slack between threads, and thus an increase in performance.

    摘要翻译： 公开了一种多线程架构，用于使用推测性内存支持在冗余多线程系统中缓存未检查的存储以进行故障检测。 特别地，SRT处理器的性能通过使用推测性内存支持来缓冲领先的线程存储来增强，直到它们可以与其尾随线程对应来进行比较。 将这些存储缓冲在存储器系统中，可以将它们从存储缓冲区中删除。 由于推测性内存系统的容量会比存储缓冲区大，所以可能会在引导线程被迫停止之前缓存附加存储。 这将导致线程之间的松弛增加，从而导致性能的提高。