公开(公告)号：US06184092B2

公开(公告)日：2001-02-06

申请号：US09444988

申请日：1999-11-23

Applicant: Mao-song Tseng ,  Rong-ching Chen ,  Su-wen Chang ,  Chin-lin Lin

Inventor： Mao-song Tseng ,  Rong-ching Chen ,  Su-wen Chang ,  Chin-lin Lin

IPC: H01L21336

Abstract: A method for forming a self-aligned contact for a trench DMOS transistor comprises: providing a semiconductor substrate; etching a trench into the semiconductor substrate at a selected location on the surface of the semiconductor substrate; forming a first dielectric layer that covers the semiconductor substrate and walls of the trench; forming a plug in the trench, which comprises a step of depositing a semiconductor layer that covers the semiconductor substrate and fills in the trench, and a step of etching the semiconductor layer until the plug is below the trench for about 0.2 to 0.3 micron; forming a second dielectric layer on the plug; and forming a conductive layer over the second dielectric layer and the surface of the semiconductor substrate for ohmic contact regions.

Abstract translation: 用于形成沟槽DMOS晶体管的自对准接触的方法包括：提供半导体衬底; 在所述半导体衬底的表面上的选定位置处将沟槽蚀刻到所述半导体衬底中; 形成覆盖半导体衬底和沟槽壁的第一介电层; 在沟槽中形成插塞，其包括沉积覆盖半导体衬底并填充在沟槽中的半导体层的步骤，以及蚀刻半导体层直到插塞在沟槽下方约0.2至0.3微米的步骤; 在所述插头上形成第二电介质层; 以及在第二电介质层和用于欧姆接触区域的半导体衬底的表面上形成导电层。

公开(公告)号：US06998315B2

公开(公告)日：2006-02-14

申请号：US11056450

申请日：2005-02-11

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0661 ,  H01L29/41766 ,  H01L29/7802

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench. A metal layer covers portions of the passivation layer on the side walls of the trench to expose a part of the passivation layer over the bottom surface of the trench.

Abstract translation: 本发明的实施例涉及一种为沟槽DMOS器件提供的终端结构，以减少由于在有源区域的边界处的电场拥挤而产生的电流泄漏及其制造方法。 在一个实施例中，沟槽DMOS器件的端接结构包括在衬底上的第一类型导电性衬底和第一类型导电性的外延层。 外延层具有比衬底更低的掺杂浓度。 在外延层内提供第二类导电体的主体区域。 沟槽延伸穿过衬底的有源区域和边缘之间的主体区域。 栅极氧化物层排列沟槽并且延伸到沟槽和有源区域之间的主体区域的上表面。 钝化层形成在栅极氧化层上，包括沟槽的侧壁和底表面。 金属层覆盖沟槽侧壁上的钝化层的部分，以使钝化层的一部分暴露在沟槽的底表面上。

公开(公告)号：US06855986B2

公开(公告)日：2005-02-15

申请号：US10652442

申请日：2003-08-28

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/772

CPC classification number: H01L29/7813 ,  H01L29/0661 ,  H01L29/41766 ,  H01L29/7802

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench. A metal layer covers portions of the passivation layer on the side walls of the trench to expose a part of the passivation layer over the bottom surface of the trench.

Abstract translation: 本发明的实施例涉及一种为沟槽DMOS器件提供的终端结构，以减少由于在有源区域的边界处的电场拥挤而产生的电流泄漏及其制造方法。 在一个实施例中，沟槽DMOS器件的端接结构包括在衬底上的第一类型导电性衬底和第一类型导电性的外延层。 外延层具有比衬底更低的掺杂浓度。 在外延层内提供第二类导电体的主体区域。 沟槽延伸穿过衬底的有源区域和边缘之间的主体区域。 栅极氧化物层排列沟槽并且延伸到沟槽和有源区域之间的主体区域的上表面。 钝化层形成在栅极氧化层上，包括沟槽的侧壁和底表面。 金属层覆盖沟槽侧壁上的钝化层的部分，以使钝化层的一部分暴露在沟槽的底表面上。

公开(公告)号：US06335260B1

公开(公告)日：2002-01-01

申请号：US09627136

申请日：2000-07-27

Applicant: Mao-song Tseng ,  Rong-ching Chen ,  Chin-lin Lin ,  Su-wen Chang

Inventor： Mao-song Tseng ,  Rong-ching Chen ,  Chin-lin Lin ,  Su-wen Chang

IPC: H01L2176

CPC classification number: H01L21/763 ,  G03F1/36

Abstract: In the invention, a photoresist layer is first spread on a semiconductor structure, and then using a photomask with a specially designed pattern exposes the photoresist layer. Next, the photoresist layer is developed to form a patterned photoresist layer. Thereafter, using the patterned photoresist layer as a mask, a trench is formed in the semiconductor structure by selective etching. The pattern of the photomask according to the invention is formed as in the following steps. At first, a first pattern extending in a first direction and having a first side and a second side that is opposite to the first side is formed. Next, a second pattern extending in a second direction that is perpendicular to the first direction is formed in such a way that an end of the second pattern is connected with the first side of the first pattern. Thereafter, a concave edge is formed on the second side to substantially face the second pattern. The distance between the first side and the second side is shortened due to the presence of the concave edge. As a result, the depth of the dimples developed at the intersection points of the dimple lines is greatly reduced when a polysilicon layer is deposited on the trench formed according to the invention.

Abstract translation: 在本发明中，光致抗蚀剂层首先在半导体结构上扩散，然后使用具有特殊设计图案的光掩模曝光光刻胶层。 接下来，将光致抗蚀剂层显影以形成图案化的光致抗蚀剂层。 此后，使用图案化的光致抗蚀剂层作为掩模，通过选择性蚀刻在半导体结构中形成沟槽。 根据本发明的光掩模的图案如以下步骤形成。 首先，形成沿第一方向延伸并具有与第一侧相反的第一侧和第二侧的第一图案。 接下来，沿着与第一方向垂直的第二方向延伸的第二图案形成为使得第二图案的端部与第一图案的第一侧连接。 此后，在第二侧上形成基本上面对第二图案的凹形边缘。 第一侧和第二侧之间的距离由于存在凹形边缘而缩短。 结果，当在根据本发明形成的沟槽上沉积多晶硅层时，在凹坑线的交点处产生的凹坑的深度大大减小。

公开(公告)号：US20050199952A1

公开(公告)日：2005-09-15

申请号：US11056450

申请日：2005-02-11

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L31/119

CPC classification number: H01L29/7813 ,  H01L29/0661 ,  H01L29/41766 ,  H01L29/7802

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench. A metal layer covers portions of the passivation layer on the side walls of the trench to expose a part of the passivation layer over the bottom surface of the trench.