公开(公告)号：US08140937B2

公开(公告)日：2012-03-20

申请号：US11969449

申请日：2008-01-04

Applicant: Shiva R. Dasari ,  Sudhir Dhawan ,  Joseph Allen Kirscht ,  Jennifer L. Vargus

Inventor： Shiva R. Dasari ,  Sudhir Dhawan ,  Joseph Allen Kirscht ,  Jennifer L. Vargus

IPC: G11C29/00

CPC classification number: G06F11/1044 ,  G11C2029/0411

Abstract: A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.

Abstract translation: 一种用于改善计算机系统的存储器中的存储器初始化的方法和装置。 存储器中的存储器单元包括多个等级，每个等级具有唯一的等级选择。 奇偶校验发生器输出与编码秩选择是否具有偶数或奇数“1”相对应的奇偶校验位。 奇偶校验位由生成ECC位的错误检查和校正（ECC）单元使用，ECC位存储在具有活动秩选择的等级中。 在存储器初始化周期的第一间隔期间，并行地初始化其编码级选择中具有偶数“1”的等级。 在存储器初始化期间的第二间隔期间，并行地初始化其编码秩选择中具有奇数“1”的等级。

公开(公告)号：US07447934B2

公开(公告)日：2008-11-04

申请号：US11168145

申请日：2005-06-27

Applicant: Shiva R. Dasari ,  Sudhir Dhawan ,  Ryuji Orita ,  Wingcheung T. Tam

Inventor： Shiva R. Dasari ,  Sudhir Dhawan ,  Ryuji Orita ,  Wingcheung T. Tam

IPC: G06F11/00

CPC classification number: G06F11/0793 ,  G06F11/0745

Abstract: A method, system, and program product for recovering from a bus error in a computer system having a hot plug interface. In accordance with the method of the present invention, an operating system transparent interrupt, such as a system management interrupt, is generated in response to a bus error. Responsive to the operating system transparent interrupt, the hot pluggable bus is scanned and a device associated with the error is identified by an interrupt handler invoked by the interrupt. Finally, a hot plug configuration manager, such as an advanced configuration and power interface is utilized to remove the identified device from system operations without having to restart the system.

Abstract translation: 一种用于从具有热插拔接口的计算机系统中的总线错误中恢复的方法，系统和程序产品。 根据本发明的方法，响应总线错误产生诸如系统管理中断的操作系统透明中断。 响应于操作系统透明中断，热插拔总线被扫描，并且与该错误相关联的设备由中断调用的中断处理程序识别。 最后，使用诸如高级配置和电源接口之类的热插拔配置管理器来将所识别的设备从系统操作中移除，而不必重新启动系统。

公开(公告)号：US20070011500A1

公开(公告)日：2007-01-11

申请号：US11168145

申请日：2005-06-27

Applicant: Shiva Dasari ,  Sudhir Dhawan ,  Ryuji Orita ,  Wingcheung Tam

Inventor： Shiva Dasari ,  Sudhir Dhawan ,  Ryuji Orita ,  Wingcheung Tam

IPC: G06F11/00

CPC classification number: G06F11/0793 ,  G06F11/0745

Abstract: A method, system, and program product for recovering from a bus error in a computer system having a hot plug interface. In accordance with the method of the present invention, an operating system transparent interrupt, such as a system management interrupt, is generated in response to a bus error. Responsive to the operating system transparent interrupt, the hot pluggable bus is scanned and a device associated with the error is identified by an interrupt handler invoked by the interrupt. Finally, a hot plug configuration manager, such as an advanced configuration and power interface is utilized to remove the identified device from system operations without having to restart the system.

Abstract translation: 一种用于从具有热插拔接口的计算机系统中的总线错误中恢复的方法，系统和程序产品。 根据本发明的方法，响应总线错误产生诸如系统管理中断的操作系统透明中断。 响应于操作系统透明中断，热插拔总线被扫描，并且与该错误相关联的设备由中断调用的中断处理程序识别。 最后，使用诸如高级配置和电源接口之类的热插拔配置管理器来将所识别的设备从系统操作中移除，而不必重新启动系统。

公开(公告)号：US5287457A

公开(公告)日：1994-02-15

申请号：US870159

申请日：1992-04-15

Applicant: Ravi K. Arimilli ,  Sudhir Dhawan ,  James O. Nicholson ,  David W. Siegel

Inventor： Ravi K. Arimilli ,  Sudhir Dhawan ,  James O. Nicholson ,  David W. Siegel

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/14 ,  G06F15/16

CPC classification number: G06F13/4027 ,  G06F13/28

Abstract: A DMA controller coupled to two separate buses controls the transfer of data between them. To effect a block data transfer, data is simultaneously read on one bus and written on the other. This allows data to be transferred between buses at the maximum transfer rate supported by the slower bus.

Abstract translation: 耦合到两个独立总线的DMA控制器控制它们之间的数据传输。 为了实现块数据传输，在一个总线上同时读取数据并写入另一个总线。 这允许以较慢总线支持的最大传输速率在总线之间传输数据。

公开(公告)号：US5109490A

公开(公告)日：1992-04-28

申请号：US297772

申请日：1989-01-13

Applicant: Ravi K. Arimilli ,  Sudhir Dhawan ,  James O. Nicholson ,  David W. Siegel

Inventor： Ravi K. Arimilli ,  Sudhir Dhawan ,  James O. Nicholson ,  David W. Siegel

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/4217 ,  G06F13/28

Abstract: A computer system can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.

公开(公告)号：US07251185B2

公开(公告)日：2007-07-31

申请号：US11064741

申请日：2005-02-24

Applicant: John M. Borkenhagen ,  Sudhir Dhawan ,  Philip R. Hillier, III ,  Joseph A. Kirscht ,  Randolph S. Kolvick

Inventor： John M. Borkenhagen ,  Sudhir Dhawan ,  Philip R. Hillier, III ,  Joseph A. Kirscht ,  Randolph S. Kolvick

IPC: G11C8/00

CPC classification number: G06F11/1666 ,  G06F11/20 ,  G06F12/0607

Abstract: In an aspect, a method is provided for using memory. The method includes the steps of (1) employing memory stacking, memory mirroring and memory interleaving in a total memory to reduce a number of memory entries that are written to an input/output (I/O) device while a portion of the total memory is replaced; and (2) storing data in the total memory. Numerous other aspects are provided.

Abstract translation: 在一方面，提供了一种用于使用存储器的方法。 该方法包括以下步骤：（1）在总存储器中采用存储器堆叠，存储器镜像和存储器交错以减少写入输入/输出（I / O）设备的存储器条目的数量，同时存储器的一部分 被替换 和（2）将数据存储在总存储器中。 提供了许多其他方面。

公开(公告)号：US20060187739A1

公开(公告)日：2006-08-24

申请号：US11064741

申请日：2005-02-24

Applicant: John Borkenhagen ,  Sudhir Dhawan ,  Philip Hillier ,  Joseph Kirscht ,  Randolph Kolvick

Inventor： John Borkenhagen ,  Sudhir Dhawan ,  Philip Hillier ,  Joseph Kirscht ,  Randolph Kolvick

IPC: G11C8/00

CPC classification number: G06F11/1666 ,  G06F11/20 ,  G06F12/0607

Abstract: In an aspect, a method is provided for using memory. The method includes the steps of (1) employing memory stacking, memory mirroring and memory interleaving in a total memory to reduce a number of memory entries that are written to an input/output (I/O) device while a portion of the total memory is replaced; and (2) storing data in the total memory. Numerous other aspects are provided.

Abstract translation: 在一方面，提供了一种使用存储器的方法。 该方法包括以下步骤：（1）在总存储器中采用存储器堆叠，存储器镜像和存储器交错以减少写入输入/输出（I / O）设备的存储器条目的数量，同时存储器的一部分 被替换 和（2）将数据存储在总存储器中。 提供了许多其他方面。

公开(公告)号：US06378027B1

公开(公告)日：2002-04-23

申请号：US09281080

申请日：1999-03-30

Applicant: Richard Bealkowski ,  Sudhir Dhawan ,  Kenneth Claude Hinz ,  Peter Matthew Thomsen

Inventor： Richard Bealkowski ,  Sudhir Dhawan ,  Kenneth Claude Hinz ,  Peter Matthew Thomsen

IPC: G06F1300

CPC classification number: G06F13/4072

Abstract: A method of servicing a processor array of a computer system by quiescing a processor selected for maintenance and removing the selected processor from a processor pool used by the computer's operating system. The selected processor is then powered down while maintaining power to and operation of other processors in the processor array. The selected processor may be identified as being defective, or may have been selected for upgrading. The processor array may include several processor clusters, such that the quiescing, removing and powering down steps apply to all processors in one of the processing clusters. The operating system assigns one of the processors in the processor array to be a service processor, and if the service processor is the processor selected for maintenance, the OS re-assigns the service processor functions to another processor in the processor array.

Abstract translation: 一种维护计算机系统的处理器阵列的方法，该方法是通过静止被选择进行维护的处理器，并从计算机的操作系统使用的处理器池中移除所选择的处理器。 然后，将所选择的处理器断电，同时维持处理器阵列中其他处理器的电源和操作。 所选择的处理器可能被识别为有缺陷的，或者可能被选择用于升级。 处理器阵列可以包括几个处理器集群，使得停顿，去除和掉电步骤适用于一个处理集群中的所有处理器。 操作系统将处理器阵列中的一个处理器分配为服务处理器，并且如果服务处理器是被选择用于维护的处理器，则OS将服务处理器功能重新分配给处理器阵列中的另一个处理器。

公开(公告)号：US5287482A

公开(公告)日：1994-02-15

申请号：US912043

申请日：1992-07-09

Applicant: Ravi K. Arimilli ,  Sudhir Dhawan ,  James O. Nicholson ,  David W. Siegel

Inventor： Ravi K. Arimilli ,  Sudhir Dhawan ,  James O. Nicholson ,  David W. Siegel

IPC: G06F12/08 ,  G06F13/00

CPC classification number: G06F12/084

Abstract: A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Virtual memory addresses used by the input/output devices are translated into real addresses in the system memory. Virtual memory can be partitioned, with some virtual addresses being mapped to a second memory attached to the input/output bus.

Abstract translation: 用于连接到输入/输出总线的输入/输出设备的缓存。 通过输入/输出设备访问系统内存的请求通过缓存。 输入/输出设备使用的虚拟内存地址将转换为系统内存中的实际地址。 可以对虚拟内存进行分区，一些虚拟地址映射到连接到输入/输出总线的第二个内存。

公开(公告)号：US20090177946A1

公开(公告)日：2009-07-09

申请号：US11969449

申请日：2008-01-04

Applicant: Shiva R. Dasari ,  Sudhir Dhawan ,  Joseph Allen Kirscht ,  Jennifer L. Vargus

Inventor： Shiva R. Dasari ,  Sudhir Dhawan ,  Joseph Allen Kirscht ,  Jennifer L. Vargus

IPC: G11C29/00 ,  G06F11/00

CPC classification number: G06F11/1044 ,  G11C2029/0411

Abstract: A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.

Abstract translation: 一种用于改善计算机系统的存储器中的存储器初始化的方法和装置。 存储器中的存储器单元包括多个等级，每个等级具有唯一的等级选择。 奇偶校验发生器输出与编码秩选择是否具有偶数或奇数“1”相对应的奇偶校验位。 奇偶校验位由生成ECC位的错误检查和校正（ECC）单元使用，ECC位存储在具有活动秩选择的等级中。 在存储器初始化周期的第一间隔期间，并行地初始化其编码级选择中具有偶数“1”的等级。 在存储器初始化期间的第二间隔期间，并行地初始化其编码秩选择中具有奇数“1”的等级。