公开(公告)号：US08786328B2

公开(公告)日：2014-07-22

申请号：US13611691

申请日：2012-09-12

Applicant: Swaminathan Sankaran ,  Sudipto Chakraborty ,  Per T. Roine

Inventor： Swaminathan Sankaran ,  Sudipto Chakraborty ,  Per T. Roine

IPC: H03K21/00

CPC classification number: H03K21/026

Abstract: An apparatus is provided. Latches are coupled in series with one another in a ring configuration. Each latch includes a tri-state inverter, a first resistor-capacitor (RC) network, and a second RC network. The tri-state inverter has a first clock terminal and a second clock terminal. The first RC network is coupled to the first clock terminal. The second RC network is coupled to the second clock terminal. A biasing network is also provided. The biasing network has a first bias voltage generator that is coupled to the first RC network for each latch and a second bias voltage generator that is coupled to the second RC network for each latch.

Abstract translation: 提供了一种装置。 锁存器以环形配置彼此串联耦合。 每个锁存器包括三态反相器，第一电阻器 - 电容器（RC）网络和第二RC网络。 三态反相器具有第一时钟端子和第二时钟端子。 第一个RC网络耦合到第一个时钟终端。 第二个RC网络耦合到第二个时钟终端。 还提供了偏置网络。 偏置网络具有第一偏置电压发生器，其耦合到用于每个锁存器的第一RC网络，以及耦合到每个锁存器的第二RC网络的第二偏置电压发生器。

公开(公告)号：US20140070853A1

公开(公告)日：2014-03-13

申请号：US13611691

申请日：2012-09-12

Applicant: Swaminathan Sankaran ,  Sudipto Chakraborty ,  Per T. Roine

Inventor： Swaminathan Sankaran ,  Sudipto Chakraborty ,  Per T. Roine

IPC: H03K21/02

CPC classification number: H03K21/026

Abstract: An apparatus is provided. Latches are coupled in series with one another in a ring configuration. Each latch includes a tri-state inverter, a first resistor-capacitor (RC) network, and a second RC network. The tri-state inverter has a first clock terminal and a second clock terminal. The first RC network is coupled to the first clock terminal. The second RC network is coupled to the second clock terminal. A biasing network is also provided. The biasing network has a first bias voltage generator that is coupled to the first RC network for each latch and a second bias voltage generator that is coupled to the second RC network for each latch.

Abstract translation: 提供了一种装置。 锁存器以环形配置彼此串联耦合。 每个锁存器包括三态反相器，第一电阻器 - 电容器（RC）网络和第二RC网络。 三态反相器具有第一时钟端子和第二时钟端子。 第一个RC网络耦合到第一个时钟终端。 第二个RC网络耦合到第二个时钟终端。 还提供了偏置网络。 偏置网络具有第一偏置电压发生器，其耦合到用于每个锁存器的第一RC网络，以及耦合到每个锁存器的第二RC网络的第二偏置电压发生器。

公开(公告)号：US08605770B2

公开(公告)日：2013-12-10

申请号：US12702628

申请日：2010-02-09

Applicant: June Chul Roh ,  Anuj Batra ,  Sudipto Chakraborty ,  Srinath Hosur

Inventor： June Chul Roh ,  Anuj Batra ,  Sudipto Chakraborty ,  Srinath Hosur

IPC: H04B1/00

CPC classification number: H04B1/69 ,  H04B1/7176 ,  H04B2001/6908

Abstract: A symbol modulation system applicable to a body area network is disclosed herein. The symbol modulation system includes a symbol mapper. The symbol mapper is configured to determine a time within a predetermined symbol transmission interval at which a transmission representative of the symbol will occur. The time is determined based on a value of a symbol and a value of a time-hopping sequence. The time is selected from a plurality of symbol value based time slots, and a plurality of time-hopping sequence sub-time-slots within each symbol value based time slot. The symbol mapper is configured to generate a single guard interval within the symbol transmission interval. The single guard interval is positioned to terminate the symbol transmission interval.

公开(公告)号：US07113008B2

公开(公告)日：2006-09-26

申请号：US11222011

申请日：2005-09-08

Applicant: Bevin George Perumana ,  Sudipto Chakraborty ,  Chang-Ho Lee ,  Joy Laskar ,  Sang-Hyun Woo

Inventor： Bevin George Perumana ,  Sudipto Chakraborty ,  Chang-Ho Lee ,  Joy Laskar ,  Sang-Hyun Woo

IPC: H03B19/00

CPC classification number: H03D7/125

Abstract: A frequency mixing apparatus is provided. In the frequency mixing apparatus, a PMOS transistor is coupled to an NMOS transistor in a cascode configuration and an LO signal is applied to the bulks of the PMOS and NMOS transistors so that an input signal applied to their gates is mixed with the LO signal. High isolation between the bulks and gates of the transistors resulting from application of the LO signal to the bulks prevents leakage of the LO signal, thereby decreasing a DC offset voltage. This renders the frequency mixing applicable to a DCR. Also, due to the cascade configuration similar to an inverter configuration, the frequency mixing apparatus can be incorporated in an FPGA of a MODEM in SDR applications. Frequency mixing based on switching of a threshold voltage decreases a noise factor and enables frequency mixing in a low supply voltage range, thereby decreasing power consumption.

Abstract translation: 提供了一种混频装置。 在频率混合装置中，PMOS晶体管以共源共栅配置耦合到NMOS晶体管，并且LO信号施加到PMOS和NMOS晶体管的体积，使得施加到其栅极的输入信号与LO信号混合。 通过将LO信号施加到体积而产生的晶体管的大块和栅极之间的高隔离防止了LO信号的泄漏，从而减小了DC偏移电压。 这使得频率混合适用于DCR。 另外，由于与逆变器配置相似的级联配置，所以可将混频装置并入SDR应用中的MODEM的FPGA中。 基于阈值电压的切换的频率混合降低了噪声因子，并且能够在低电源电压范围内进行频率混合，从而降低功耗。

公开(公告)号：US20100202494A1

公开(公告)日：2010-08-12

申请号：US12702628

申请日：2010-02-09

Applicant: June Chul ROH ,  Anuj BATRA ,  Sudipto CHAKRABORTY ,  Srinath HOSUR

Inventor： June Chul ROH ,  Anuj BATRA ,  Sudipto CHAKRABORTY ,  Srinath HOSUR

IPC: H04B1/00

CPC classification number: H04B1/69 ,  H04B1/7176 ,  H04B2001/6908

Abstract: A symbol modulation system applicable to a body area network is disclosed herein. The symbol modulation system includes a symbol mapper. The symbol mapper is configured to determine a time within a predetermined symbol transmission interval at which a transmission representative of the symbol will occur. The time is determined based on a value of a symbol and a value of a time-hopping sequence. The time is selected from a plurality of symbol value based time slots, and a plurality of time-hopping sequence sub-time-slots within each symbol value based time slot. The symbol mapper is configured to generate a single guard interval within the symbol transmission interval. The single guard interval is positioned to terminate the symbol transmission interval.

Abstract translation: 本文公开了适用于体区网络的符号调制系统。 符号调制系统包括符号映射器。 符号映射器被配置为确定符号的传输代表将发生的预定符号传输间隔内的时间。 该时间基于符号的值和跳时序列的值来确定。 该时间是从基于多个符号值的时隙中选出的，以及在每个基于符号值的时隙内的多个跳时序列子时隙。 符号映射器被配置为在符号传输间隔内产生单个保护间隔。 单个保护间隔定位成终止符号传输间隔。

公开(公告)号：US20100164688A1

公开(公告)日：2010-07-01

申请号：US12347652

申请日：2008-12-31

Applicant: Sudipto CHAKRABORTY

Inventor： Sudipto CHAKRABORTY

IPC: H04Q5/22

CPC classification number: A61N1/37252 ,  H02J7/025 ,  H02J17/00 ,  H02J50/20 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/02 ,  H04Q2213/13003

Abstract: In at least some embodiments, an auxiliary device compatible with a biomedical implantable comprises a first transceiver and a controller coupled to the first transceiver. If the first transceiver receives a wireless data signal from an implantable unit, the controller generates a corresponding data signal for transmission to a wireless network. The corresponding data signal has at least one of a higher power level and a higher frequency band compared to the wireless data signal.

Abstract translation: 在至少一些实施例中，与生物医学可植入装置兼容的辅助装置包括耦合到第一收发器的第一收发器和控制器。 如果第一收发器从可植入单元接收无线数据信号，则控制器产生相应的数据信号以传输到无线网络。 与无线数据信号相比，对应的数据信号具有较高功率电平和较高频带中的至少一个。

公开(公告)号：US20060057998A1

公开(公告)日：2006-03-16

申请号：US11222011

申请日：2005-09-08

Applicant: Bevin Perumana ,  Sudipto Chakraborty ,  Chang-Ho Lee ,  Joy Laskar ,  Sang-Hyun Woo

Inventor： Bevin Perumana ,  Sudipto Chakraborty ,  Chang-Ho Lee ,  Joy Laskar ,  Sang-Hyun Woo

IPC: H04B1/18

CPC classification number: H03D7/125

Abstract: A frequency mixing apparatus is provided. In the frequency mixing apparatus, a PMOS transistor is coupled to an NMOS transistor in a cascode configuration and an LO signal is applied to the bulks of the PMOS and NMOS transistors so that an input signal applied to their gates is mixed with the LO signal. High isolation between the bulks and gates of the transistors resulting from application of the LO signal to the bulks prevents leakage of the LO signal, thereby decreasing a DC offset voltage. This renders the frequency mixing applicable to a DCR. Also, due to the cascade configuration similar to an inverter configuration, the frequency mixing apparatus can be incorporated in an FPGA of a MODEM in SDR applications. Frequency mixing based on switching of a threshold voltage decreases a noise factor and enables frequency mixing in a low supply voltage range, thereby decreasing power consumption.